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UVM (Pre-IEEE) Methodology and BCL Forum

Forum for posting questions about the pre-IEEE UVM library and its application to verification environments. 

944 topics in this forum

  1. check while adding multiple fields with same name in same register

    By piyunaffi,
    • 0 replies
    • 286 views

  2. How to do two bus2reg operations for a single transaction

    By mon,
    • 2 replies
    • 733 views

  3. [Cadence] UVM-ML compiling issue with xcelium

    By hyperion007,
    • 1 reply
    • 535 views

  4. Register write() clobbers simultaneous access in multi-threaded testbench

    By jeremyr,
    • 2 replies
    • 1.8k views

  5. UVM Backdoor access

    By Bazinga24,
    • 0 replies
    • 983 views

  6. get after write doesn't update desired value, mirror gets updated correctly on read

    By Ai_Ar,
    • 0 replies
    • 560 views

  7. `uvm_field_queue_object macro cause compiler error

    By ysimhony,   
    • 1 reply
    • 992 views

  8. UVM IEEE v1.1 kill() and m_kill()

    By DV-E,
    • 0 replies
    • 732 views

  9. multiple threads calling sequencer lock results in deadlock

    By Lawrence Said,   
    • 2 replies
    • 1.2k views

  10. sequencer grab/ungrab not behaving according to specs

    By StefanoEsposito,
    • 1 reply
    • 1.2k views

  11. get_starting_phase() vs starting seq with uvm_config_db

    By DV-E,
    • 0 replies
    • 3.3k views

  12. Address Map as submap to multiple address maps

    By Anil Kumar,   
    • 2 replies
    • 4.1k views

  13. set_type_override and set_inst_override usage inconsistency

    By chintanm86,
    • 2 replies
    • 4k views

  14. UVM factory usage recommendation inconsistent with base class implementation.

    By aelms,
    • 0 replies
    • 983 views

  15. uvm_comparer::compare_field_int() False Pass with size

    By aelms,
    • 1 reply
    • 1.2k views

  16. UVM Reg Model: access register error using bitbash seq because of predictor

    By cuonghl,
    • 3 replies
    • 3.6k views

  17. How to send sequence instead of stream of sequence_item?

    By soloist_huaxin,
    • 0 replies
    • 824 views

  18. uvm_object::set_int_local for static integer array

    By Robert.g.Liu,
    • 1 reply
    • 1.9k views

  19. Two sequences getting sequencer.lock grant in the same simulation cycle

    By b0rna,   
    • 0 replies
    • 2k views

  20. UVM register model: Field access and bus2reg

    By joniale,   
    • 2 replies
    • 7.4k views

  21. UVM register access with multiple masters to same register model

    By qwerty,
    • 3 replies
    • 2.6k views

  22. How to set a virtual interface of a VIP from SoC tb top

    By rudra2255,   
    • 0 replies
    • 1.4k views

  23. What would be the strategy to verify

    By karandeep963,
    • 1 reply
    • 1.4k views

  24. uvm_mem depth configuration

    By qwerty,
    • 1 reply
    • 1.4k views

  25. Problem about Setting UVM severity

    By thanhvanchi,
    • 1 reply
    • 2.2k views
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