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hbhbts

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  1. the original compare_field_int() is plan to bit size <=64, you can use compare_field() instead.
  2. based on your defined data_item, your monitor implementation is incorrect. the monitor shall sample the sample the in signal and than sample the corresponding out signal, give the encapsulation the two value in a data item, send it out.
  3. you can use the one monitor for the dut input and output. And i think the root case is not base on how mant input/ouput of dut you have, but the interface type the dut have. for exanple, if you have one axi input and one aix output, you can use one monitor to collect all input/outout axi transaction. So i think the number monitor is based on the types of interfaces.
  4. as you define a domain1 phase with the run_phase, so when the run_phase complete, extract phase will scheduled for last phase to run. at the same time, the domain1 phase also complete and schedule extract phase to next to run. So the there two phase to printed. for your second question, the run phase schedule extract phase and the domain1 phase schedule final phase and clean the pahse runining before the final so final phase run once.
  5. add a TLM port in regular driver and the port is used to get the transaction and sent to ref model. And also the driver respondsiable for transition the item to RTL signals
  6. maybe you not enable polymorphism at other functions when extend from base class.
  7. you can enable UVM_PHASE_TRACE, this debug message can print phases and objections information.
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