Jump to content

UVM SystemVerilog Discussions

Use this forum when your question is about SystemVerilog language issues in the context of UVM. These can be about how to use a language feature is user code with the UVM or about language usage inside the UVM BCL.

596 topics in this forum

  1. difference between ovm_sequence & uvm_sequence

    By vishal,
    • 1 reply
    • 1.6k views

  2. Need help migrating VMM to UVM

    By vjdivya,
    • 0 replies
    • 1.7k views

  3. Unable to set object and retrive it when needed.

    By Bala,
    • 2 replies
    • 4.3k views

  4. UVM Register write_reg read_reg

    By apayal,
    • 2 replies
    • 3.5k views

  5. Register Package: get_mem_by_offset

    By uvm_rookie,
    • 3 replies
    • 3.1k views

  6. Illegal assignment to class type uvm_component [...]from class type [...]

    By vvs3693,
    • 2 replies
    • 2.4k views

  7. uvm_config_db and arrays

    By saxmanlogic,
    • 1 reply
    • 8.7k views

  8. DPI C++ Exported functions

    By zhon1231,
    • 1 reply
    • 6.7k views

  9. declarative vs procedural constraints

    By ash123,
    • 3 replies
    • 3.7k views

  10. Driving Internal DUT Interfaces

    By calvapete,
    • 7 replies
    • 4.8k views

  11. how to check the set_type_overide is right

    By dmq0420,
    • 2 replies
    • 1.9k views

  12. Parameterized Designs

    By zhon1231,
    • 4 replies
    • 2.6k views

  13. How to get configuration info from UVM Env back to SV testbench?

    By wavy,
    • 1 reply
    • 1.6k views

  14. Adding Contraints in Driver?

    By ganeshts,
    • 11 replies
    • 4.5k views

  15. Accessing a base test class data element in an extended class.

    By bap001,
    • 4 replies
    • 2.9k views

  16. UVM RAL memory access

    By aobula,
    • 1 reply
    • 4.9k views

  17. Randomization a few used values with dist

    By ryz,
    • 2 replies
    • 7.7k views

  18. Overriding virtual functions in parameterized classes

    By Erling,
    • 2 replies
    • 2k views

  19. implementing reactive slave agent in uvm

    By vgampa,
    • 6 replies
    • 8.1k views

  20. how can I acess the uvm_reg_block component directly in the virtual sequence?

    By kdw0912,
    • 1 reply
    • 2.4k views

  21. vlog 7027

    By Disha,
    • 1 reply
    • 3.1k views

  22. error : near uvm_test unexcepted identifier

    By Disha,
    • 1 reply
    • 2.2k views

  23. Parameterized Clases

    By zhon1231,
    • 1 reply
    • 1.9k views

  24. how to randomize local variable for every new transaction with uvm_do_with

    By aputcha,
    • 4 replies
    • 9.5k views

  25. UVM way of passing information from a monitor to a sequence inside of the same agent?

    By frodus,
    • 1 reply
    • 3.6k views
×
×
  • Create New...