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Parameterized Designs

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Hi all,

I have a quick question regarding parameterized designs. In my testbench I am initializing a DUT that requires a parameter called BIT_WIDTH. Is there any way to initialize the DUT's BIT_WIDTH using a command line argument?

For example, is the following possible?

vcs .... +COMMAND_LINE_BIT_WIDTH=10....

module top





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thanks for the reply! pvalue looks like what I need. But it does not seem to be working though.

On my vcs command, I added "-pvalue param1=2", but I keep getting "cross module reference errors".

param1 is defined in my top level package.

package top_pkg;

parameter param1 = 4;

import top_pkg::*;

module top;

dut #(.x (param1)) dut1(...);

Any ideas on fixing this?

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