Parameterized Designs

[zhon1231]

Hi all,

I have a quick question regarding parameterized designs. In my testbench I am initializing a DUT that requires a parameter called BIT_WIDTH. Is there any way to initialize the DUT's BIT_WIDTH using a command line argument?

For example, is the following possible?

vcs .... +COMMAND_LINE_BIT_WIDTH=10....

module top

Design #(.BIT_WIDTH(COMMAND_LINE_BIT_WIDTH)) dut (...);

...

Thanks,

Billy

[calvapete]

Pop the parameter in a package, compile it before the test_harness.

package pkg;

localparam BIT_WIDTH = 10;

endpackage

module th;

DUT #(pkg::BIT_WIDTH) dut();

...

endmodule

class env;

int bit_width = pkg::BIT_WIDTH;

...

endclass

[zhon1231]

Thats my current approach right now. But the bad part is that I have to manually change the contents of the package in order to change the parameters. Is there a way for the package to use the command line arguments?

[sacjin1123]

you can use "+pvalue dut.BIT_WIDTH=value "

[zhon1231]

thanks for the reply! pvalue looks like what I need. But it does not seem to be working though.

On my vcs command, I added "-pvalue param1=2", but I keep getting "cross module reference errors".

param1 is defined in my top level package.

package top_pkg;

parameter param1 = 4;

import top_pkg::*;

module top;

dut #(.x (param1)) dut1(...);

Any ideas on fixing this?