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  1. class txn; rand int size; rand int length; rand bit [31:0] addr; end class class my_seq extends base_seq rand bit [31:0] total_bytes; <----------------- this is a local variable virtual task body() for (int i=1; i< sequence_length; i++) begin `uvm_do_with(req, { size inside {0, 1, 2}; length inside {[0:15]}; total_bytes == ((1<<size) * (length+1)); <----------------- gives constraint inconsistancy failure }) end // for loop endtask: body endclass: my_seq
  2. For anybody who might have the questions... For now I found a work around for my problem, by passing the name of the sequence on the cmdline as a plus arg and using that with factory.find_by_name(var) as in uvm_config_db#(uvm_object_wrapper)::set(this, "*.sequencer.run_phase", "default_sequence", factory.find_by_name(default_seq));
  3. Do you know for sure that I can set the default sequence from command line by specifying the name itself with set_config_string? I was reading in a document which said that String based default sequence, set_config_string(<inst>,”default_sequence”,<seq>) is deprecated. Instead type is used. change to uvm_config_db#(uvm_object_wrapper)::set(this, “seqr.run_phase”,“default_sequence”, myseq::type_id::get()); Do you know how to set it from command line?
  4. I tried setting the default seq from command line: +uvm_set_config_string=uvm_test_top.evt1_top_env0.axi_top.axi_system_env.master[0].sequencer.run_phase,default_sequence,axi_intermediate_master_sequence::type_id::get() I also tried escaping the string as -s_opt \+uvm_set_config_string\=uvm_test_top\.evt1_top_env0\.axi_top.axi_system_env.master[0]\.sequencer\.run_phase,default_sequence,axi_intermediate_master_sequence\:\:type_id\:\:get\(\). None of them work. I get the error.. no matches found: +uvm_set_config_string=uvm_test_top.evt1_top_env0.axi_top.axi_system_env.master[0].sequencer.run_phase,default_sequence,axi_intermediate_master_sequence::type_id::get. Does anybody see what's wrong with this?
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