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UVM SystemVerilog Discussions

Use this forum when your question is about SystemVerilog language issues in the context of UVM. These can be about how to use a language feature is user code with the UVM or about language usage inside the UVM BCL.

596 topics in this forum

  1. Register backdoor write getting overwritten at next clock edge

    By johnrossserco,
    • 2 replies
    • 1.5k views

  2. pack function

    By meenu,
    • 4 replies
    • 5.3k views

  3. uvm register coverage

    By sachint,
    • 0 replies
    • 1.5k views

  4. uvm_register_sequence

    By venravi,
    • 2 replies
    • 1.8k views

  5. [virtual interface] Is is possible to pass one signal by task argument ?

    By light12,
    • 3 replies
    • 7k views

  6. derived sequencer and derived sequence. Confusion how to get sequencer handle

    By preet723,
    • 6 replies
    • 3.6k views

  7. Verify shared address map with stand-alone and unified enable signals by RGM or REG?

    By leo_chen,
    • 6 replies
    • 2.5k views

  8. Ensuring users call super.function()

    By mastrick,
    • 4 replies
    • 2.9k views

  9. Backdoor access in uvm scoreboard

    By deepamt,
    • 0 replies
    • 1.5k views

  10. calling run_test() at no-zero time

    By jithinraj1989,
    • 3 replies
    • 4.5k views

  11. packet transactions are generated by scheduler, need help with sequence class

    By preet723,
    • 7 replies
    • 7.6k views

  12. Random stability in uvm_reg

    By ccherich,
    • 0 replies
    • 1.8k views

  13. set_global_timeout

    By uvm_rookie,
    • 8 replies
    • 16.1k views

  14. generate block

    By IChip,
    • 5 replies
    • 13.1k views

  15. Problems with set_type_override_by_type for transactions

    By cliffc,
    • 1 reply
    • 5.5k views

  16. Help me! SV attributes application, who can tell me the usage of attributes? Thanks!

    By chx,
    • 2 replies
    • 2.8k views

  17. Unable to downgrade messaging severity from uvm_component

    By ian.keses@idt.com,
    • 5 replies
    • 8.9k views

  18. Possible minor bug in uvm_config_db

    By Chris Burns,
    • 1 reply
    • 1.5k views

  19. Accessing a memory element inside a memory model.

    By bap001,
    • 1 reply
    • 5.5k views

  20. Constraining a dynamic array in UVM sequence

    By niks007,
    • 4 replies
    • 5.3k views

  21. Errors in compilation of "uvm.sv"

    By kennethhar,
    • 3 replies
    • 8.1k views

  22. how to import vera file to uvm project?

    By creepsheep,
    • 2 replies
    • 2.4k views

  23. Deprecated code inside UVM_RGM 2.5

    By deshiashish,
    • 8 replies
    • 5.8k views

  24. how to override classes inside a specific class (not a specific instance)

    By LiorKoren,
    • 2 replies
    • 1.9k views

  25. uvm_rgm_2.7 won't compile

    By wavy,
    • 5 replies
    • 3.4k views
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