implementing reactive slave agent in uvm

[vgampa]

Hi,

I would like to implement reactive slave agent ,where it will drive the transaction by its own.

Which means it doesn't have a sequencer and sequences.

Does any one have an idea on implementing the same.

Thanks,

vgampa

[uwes]

hi,

why does it not have a sequencer? why does it not use sequences?

reactive agents can use the same sequencer/sequence infrastructure and can can be therefore controlled the same way as pro-active agents.

eventually the only differences typically are:

- reactive sequences typically do not use objections (because the test /pro active agents control the end of test)

- reactive sequences are typically infinite (because they have to respond at any time)

/uwe

[vgampa]

Thanks for the reply.

If the sequencer and sequences need to be there, then where do we need to implement the mechanism which sends the sequences to the sequencer.

Does the mechanism to be part of the agent.

For eg. ahb slave which is having memory inside it and its job is to update the memory whenever write happens and drive the read data in case of reads. So if this ahb slave needs to have sequencer and sequence then the mechanism where (does it needs to be part of agent or sub environment) it updates the memory or reads from the memory and sends the sequence to the sequencer.

[uwes]

hi,

>If the sequencer and sequences need to be there, then where do we need to implement the mechanism which sends the sequences to the sequencer.

it is not mandatory the reactive agents use sequences. its just good practice to use the same infrastructure.

>Does the mechanism to be part of the agent.

typically yes.

>For eg. ahb slave which is having memory inside it and its job is to update the memory whenever write happens and drive the read data in case of reads. So if this ahb slave needs to have sequencer and sequence then the mechanism where (does it needs to be >part of agent or sub environment) it updates the memory or reads from the memory and sends the sequence to the sequencer.

have a look at the ubus slave infrastructure and the slave_memory_seq. it should be simple to adapt the concept the ahb

/uwe

[vgampa]

Thanks.

I have looked at the example.

In the example, the memory was defined and used inside the sequence. But we would like to access this memory through back door access.

Is it better to have backdoor methods in the sequences and access the same from the checker/scoreboard.

[rojain]

hi,

i am working on a scenario where i need to have multiple ports in a driver where each port is connected to a different sequencer.

it is something like this...

driver.seq_item_port1.connect(sequencer.seq_item_export);

driver.seq_item_port2.connect(sequencer2.seq_item_export);

driver.seq_item_port3.connect(sequencer3.seq_item_export);

so i would use:

seq_item_port1.get_next_item(t1);

seq_item_port2.get_next_item(t2);

is this a valid connection?

if yes how to declare multiple ports in a driver?

Thanks,

Rohit

[rojain]

hi,

i am having a scenario where i am having multiple ports in the driver and each port is connected to different sequencers something like this :

driver.seq_item_port1.connect(sequencer1.seq_item_export);

driver.seq_item_port2.connect(sequencer2.seq_item_export);

i am having a sequence which is generating some transactions t1,t2,t3 ....

i want transaction t1 to go to sequencer1 and t2 to go to sequencer2.

There is "send_request(req)" method in the sequence which will send the transaction to the sequencer.

how to use this method and send the transaction to the specific sequencer?

Thanks,

Rohit

Edited December 5, 2011 by rojain