aobula Posted November 17, 2011 Report Share Posted November 17, 2011 Hi, We are using UVM-1.1 and trying to deploy RAL for modelling memory/register space. We have to implement a write to a slave module (memory write) where the interface width (64) is smaller than the memory width(512). The transactions will have a single address phase and a multiple data phases. We have multiple memory with different widths (64, 128, 256, 512 etc). For a memory with width 256 should have one address phase and 4 data phase, anything other than 4 data phase is illegal transaction. So the ral mem is modelled as 256 bits wide and the default map is set as 64bit . When calling model.mem.write(), the "do_bus_write" task inside uvm_reg_map.svh is splitting the memory width (say 256 bit) data to multiple data of 64 bits (set in default map) and address cycles. These appear in the executeSingle task in the adapter as four individual transactions and we are not able to interpret it as a part of a burst (access to a memory width of 256) or 4 individual access to memory/register width of 64. So, in the RAL adapter file, we would like to see the data as such (not split up to multiple transactions) so that we could implement the driver accordingly. Is there any way (functions to be overridden/callbacks/flags ??) to get this behavior? Thanks, Akilesh Quote Link to comment Share on other sites More sharing options...
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