UVM Register write_reg read_reg

[apayal]

From my testbench i get address where i need to do register write.

will get_reg_by_offset will help me to get the handle of the register in the format .

model.reg_name format ?

because in write_reg task i need to pass register name in this format.

[janick]

The register classes abstract the address away so you don't need to know the address. You can simply do blk.subblk.reg.write(status, 'hDEADBEEF);

[apayal]

Yes i understand that I dont need to know addess and i can write data with the register name only.

But in our env we get write/read request from the other device.

And in my env i get excet full address for writing the data.

Now based on the address i want to do register write using register sequence.

Now is there any task/fucntion to convert the full address to blk.subblk.reg ?

because for doing read/write i need to give in format

blk.subblk.reg.write(status, 'hDEADBEEF); //

or write_reg(blk.subblk.reg , status, 'hDEADBEEF );

else I will have to manually create an handle blk.subblk.reg from the address i have received.

The register classes abstract the address away so you don't need to know the address. You can simply do blk.subblk.reg.write(status, 'hDEADBEEF);