dave_59

Where did you read 0 is not a valid seed?

There have been some improvements to the performance of the field automation macros, but I still do not believe their benefit is worth the cost. You should be able to prove it to yourself by creating a simple testbench with and without the macros.

This because you need to understand the macro `uvm_oject_utils() See parameterized-classes-static-members-and-the-factory-macros, then look at the Reference for uvm_object_registry.

This is the correct functionality. There is a random number generator (RNG) for every module instance in your design, and it is seeded with a RNG from the module instance it starts from. All all modules instances start out with identical seeds. Every thread that starts inside a module instance grabs a new RNG. Threads in parallel blocks get seeded in declaration order, not in the indeterminate order they might actually start. Objects that get constructed get seeded with an RNG from the thread calling the constructor.
 
This random stability model has a few problems that the UNM attempts to correct by using a path name as an initial seed. You just need to make sure your path names are unique enough to generate distinctive seeds. A good paper to read on this topic is: Random Stability, Don't leave it to chance.

You can use a do-while loop:
module top;    //typedef enum {alpha=0, beta=1, gamma=2, delta=3, epsilon=4} greek;  //to show default assignments    typedef enum {alpha, beta, gamma, delta, epsilon} greek;    greek letters;        initial begin       $display("****** Walk thru an enumeration example. ***********");       letters = letters.first;       do begin          $display(" %0d *** %0s", letters, letters.name);      letters = letters.next;       end       while (letters != letters.first);   end endmodule : top

You use fork/join_any statements when you want to create a number of time consuming processes and block waiting for one of them to finish. You create two processes, but they do not bloc - the finish immediately because they have fork/join_none statements in them . What you probably meant was something like
 
initial begin
   me[0] = 1;
   me[1] = 2;
   me[2] = 3;
   repeat(5) begin : repeat_loop
      fork begin : b1
         foreach(me)
           fork automatic int id = me; print_value (10+id,id); join_none
        wait fork;
      end : b1
      begin :b2
          foreach(me)
            fork automatic int id = me; print_value (20+id,id); join_none
         wait fork;
       end : b2
      join_any
      disable fork;
      $display(" Disable Fork ");
      end :repeat_loop
   $display("@%g Came out of fork-join", $time);
   #20 $finish;
end // initial begin
 

You use fork/join_any statements when you want to create a number of time consuming processes and block waiting for one of them to finish. You create two processes, but they do not bloc - the finish immediately because they have fork/join_none statements in them . What you probably meant was something like
 
initial begin
   me[0] = 1;
   me[1] = 2;
   me[2] = 3;
   repeat(5) begin : repeat_loop
      fork begin : b1
         foreach(me)
           fork automatic int id = me; print_value (10+id,id); join_none
        wait fork;
      end : b1
      begin :b2
          foreach(me)
            fork automatic int id = me; print_value (20+id,id); join_none
         wait fork;
       end : b2
      join_any
      disable fork;
      $display(" Disable Fork ");
      end :repeat_loop
   $display("@%g Came out of fork-join", $time);
   #20 $finish;
end // initial begin
 

The syntax is
assert (         randomize(index) with { index inside { [1:5] } ;  }          ) else begin It's the same {} as if you wrote named constraint block. Each constraint within the {} needs to be terminated with a semi-colon
constraint range_constraint                                { index inside { [1:5] } ;  }            

Use *_hier to set all components below the top level. (I don't know why they abbreviated hierarchy)
uvm_top.set_report_default_file_hier(log_file); uvm_top.set_report_severity_action_hier (UVM_INFO, UVM_DISPLAY | UVM_LOG);

You can use a do-while loop:
module top;    //typedef enum {alpha=0, beta=1, gamma=2, delta=3, epsilon=4} greek;  //to show default assignments    typedef enum {alpha, beta, gamma, delta, epsilon} greek;    greek letters;        initial begin       $display("****** Walk thru an enumeration example. ***********");       letters = letters.first;       do begin          $display(" %0d *** %0s", letters, letters.name);      letters = letters.next;       end       while (letters != letters.first);   end endmodule : top

There certainly is a way around it.  Don't use `uvm_do_* and instead do
 
start_item(req);
req. tx_err_bytes.rand_mode(0);
req. tx_err_bytes = {4,5,7};
req.randomize() with   { tx_data_byte[0]=='h00;
                                     tx_data_byte[1]=='h11;                                      tx_data_byte[2]=='h00;                                      tx_data_byte[3]=='h99;                                      tx_data_byte[4]=='h55;                                      ///-----------------                                      tx_no_of_bytes_to_send ==20;
}
finish_item(req);

The iff clause is an edge qualifier. It means wait for the edge to happen if and only if both the edge happens AND the expression is true.
@(event iff (expression)); is equivalent to
do @event; while (!expression) This becomes very handy when using clocking blocks. Once you start using clocking blocks, you want to make sure all your code that references the clocking block signals are synchronized with the clocking block event and no other events controls or wait statements. This eliminates all chances of race conditions that might add or miss a clocking block cycle.

The best method is not to use the macros at all. Learn the basics without the use of the macros. See http://verificationhorizons.verificationacademy.com/volume-7_issue-2/articles/stream/are-ovm-and-uvm-macros-evil-a-cost-benefit-analysis_vh-v7-i2.pdf

This because you need to understand the macro `uvm_oject_utils() See parameterized-classes-static-members-and-the-factory-macros, then look at the Reference for uvm_object_registry.

You problem with the qverilog command is with the -R switch. To pass multiple arguments to the simulator, you need to include them in quotes, or whatever your shell requires to form a single argument. In either case, you should not be compiling the UVM source or DPI yourself.

The import statement only makes symbols visible inside the scope of the import. Your import statement is inside a generate block and does not make symbols visible after the generate.
 
If you need to select this package globally, it might be better to have two different versions of the same package compiled into separate libraries. Then just select the library you want at compilation time.
 
If the package only contains parameter values, then you might consider using a structure or class type as a container for your parameters instead of a package.

The import statement only makes symbols visible inside the scope of the import. Your import statement is inside a generate block and does not make symbols visible after the generate.
 
If you need to select this package globally, it might be better to have two different versions of the same package compiled into separate libraries. Then just select the library you want at compilation time.
 
If the package only contains parameter values, then you might consider using a structure or class type as a container for your parameters instead of a package.

The import statement only makes symbols visible inside the scope of the import. Your import statement is inside a generate block and does not make symbols visible after the generate.
 
If you need to select this package globally, it might be better to have two different versions of the same package compiled into separate libraries. Then just select the library you want at compilation time.
 
If the package only contains parameter values, then you might consider using a structure or class type as a container for your parameters instead of a package.

This is the correct functionality. There is a random number generator (RNG) for every module instance in your design, and it is seeded with a RNG from the module instance it starts from. All all modules instances start out with identical seeds. Every thread that starts inside a module instance grabs a new RNG. Threads in parallel blocks get seeded in declaration order, not in the indeterminate order they might actually start. Objects that get constructed get seeded with an RNG from the thread calling the constructor.
 
This random stability model has a few problems that the UNM attempts to correct by using a path name as an initial seed. You just need to make sure your path names are unique enough to generate distinctive seeds. A good paper to read on this topic is: Random Stability, Don't leave it to chance.

Everything is passed by value in a fifo. It just so happens that the value of a class variable is a handle that references a class object.
Unless you construct or clone a new object each time you write to the fifo, you are writing a handle to the same object over and over again.
 
Dave

I would rather you not use anything other than run_phase() and instead use standard OOP practice of overriding the run_phase.

Where did you see this?
 
The SystemC -> AVM -> OVM -> UVM methodologies have gone to great efforts to get everyone using a common messaging system. It's not just the Verbosity - it's all the the filters, catchers, and callback mechanisms around the messaging system that are subverted when you use $display. Many tool vendors have instrumented the UVM reporting mechanism to interact with their debugging environments, and using simple $displays will also subvert those efforts.
 
Dave

A `define macro is part of the compilation unit and does not belong to any package or other scope. Compiler directives like `define and `ifdef are compiled away as the first step in compilation process before any SystemVerilog syntax is parsed.
 
I would use an actual Verilog parameter inside a package rather than a const variable because parameters can be used in more places than variables; like range declarations. I have a DVCon paper that has a section on explaining the difference between parameters and const variables.

You can usually get more verbose help about an error message from Questa by typing verror NNNN
In this case type verror 3601.

Regardless of the direct answer to your question, I suggest that you not use an immediate assertion to check the result of randomize() and instead use a simple if/else statement. This is because assertions are included the coverage statistics for the design, and this check does not belong with the design, it is part of the testbench. 
 
If you do plan to turn off assertions, I suggest that you apply it to a specific DUT scope instead of globally to the entire simulation. You can also use the new $assertcontrol system task to only target concurrent assertions. Using both these suggestions will ensure that you do not lose the randomize functionality no matter what your tool decides to do.