gbbrown Posted May 16, 2014 Report Share Posted May 16, 2014 I have a module defined as follows... module dut(); int i; initial begin i = $urandom_range(0, 500); $display("The value of i is %1d", i); end endmodule // dut I'm trying to randomize the value assigned to the variable i. My top level module is module top_tb; dut dut_a(); dut dut_b(); dut dut_c(); endmodule When I simulate this, the output shows the same value for all three instances. # The value of i is 3 # The value of i is 3 # The value of i is 3 This is a simple example. I've tried other approaches, including placing the random variable inside a class, declaring a new object of that class inside the initial block and then randomizing the object. That yields the same result, all the values are the same in the different instances. I've added time before the randomization via a #10 statement. Same result. It seems to be related to the initial block. So how does the SystemVerilog random functions work in regards to an initial block and non-initial blocks? There some part of how those functions work that I'm not understanding. How could I set a different random value inside each dut instance within the initial block? gb Quote Link to comment Share on other sites More sharing options...
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