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Everything posted by dave_59

  1. The link answers the question on how to apply a distribution to any set of constraints. The dist construct only works with explicit values.
  2. https://verificationacademy.com/forums/systemverilog/distributed-weightage-constraint#reply-46525
  3. You always incur overhead for automation. Performance rapidly deteriorates as you introduce dependencies with other random variables. For example, suppose you need 8 unique values between 10 and 20. You are going be calling $urandom_range many extra times throwing away values that don't meet the constraints. And it becomes very difficult to know when there are no solutions, and you end up in infinite loops looking for solutions that are very hard to find or don't exist. This is what a constraint solver does for you. Since constraints are tied to the class inheritance system, they provide another key benefit: you can add to or override them easily. It's very difficult to override constraints embedded within procedural code (this includes using in-line constraints).
  4. Give your error message a unique ID. Use set_report_severity_id_override to change the severity of that ID from UVM_ERROR to UVM_INFO. Then call get_id_count at the end of your test to make sure it's non-zero.
  5. The return code usually indicates successful completion of the tool and is unrelated to completion of the test. Non-zero return codes would be OS specific error codes. The SystemVerilog standard way of indicating pass/fail status is using the $info/$warning/$error/$fatal messages. Most tools are essentially catch the UVM reports and convert them to one of the SystemVerilog messages. They also have a way of detecting the most severe message issued during a run and you can use that information for determining pass/fail status.
  6. This was recently discussed here. The assertion should fail because disable_assert is false at the start of the attempt.
  7. Works for me in Questa, and in the VCS on edaplayground.com. I mean I get no compilation errors, did not check the functionality of your code. Maybe you are using an older version, Also, I suggest using *.SystemVerilog as file extension of using *.v and -sverilog switch. That helps keep legacy Verilog files working.
  8. It is the name of a class typedef added by the `umm_object_utils or `umm_component_utils factory macros and you are using type_it::create() to access a static method in that class. I explain the macro in this blog post. I explain how the UVM implements the factory in more detail in my SystemVerilog OOP for UVM course.
  9. You could extend your class from uvm_report_object. But this also creates a uvm_report_handler object which has a lot of overhead. A few other options are Avoid using a nested class. What is it doing for you in this situation? Define the class bar at the same level as foo. Avoid using the `uvm_field macros - also a lot of overhead.
  10. You might want to see http://forums.accellera.org/topic/1967-problems-with-starting-phase/
  11. New link to mantis issue https://accellera.mantishub.io/view.php?id=4969
  12. The original intent of the phases in the OVM was to help with the initialization and shutdown of a simulation. The OVM phases mimic what happens in other environments like SystemC. end_of_elaboration is after all the elements of your testbench are constructed, and start_of_simulation is the initialization of your testbench. The phases make good breaking points for debug and checkpoints for restoring. The problem with phases in general is that unless you get everyone to universally agree on what goes in each phase, they lose their effectiveness.
  13. I think the problem is with EDAplayground.com appending extra characters at the end of each line. Look carefully at the error messages coming from each tool and you'll see a good explanation of the problem. I believe Aldec is incorrectly ignoring that extra character, so it appears that it is "working".
  14. This works for me in Modelsim/Questa. Note that the newline has been escaped and the resulting string will be displayed as a single line. If you want a newline embedded in the string, you need to add \n.
  15. Hi Linc, No to your first query. There is a difference when interacting with clocking block inputs ##0 delays. The clocking block event cb1 is guaranteed to happen after the clocking block inputs have been updated with sampled values,and ##0 will never block. My general rule when you have a process interacting with clocking block inputs and outputs, always synchronize that process to the clocking block event. And yes to your second query, unless a clocking block output is driving an input to the interface.
  16. Use uvm_config_db#(BaseA)::set() to match the uvm_config_db#(BaseA)::get() Then you need to test the result of the $cast to know if the object was overridden or not.
  17. It's an artifact of the UVM implementation that stores the children (siblings) in an associative array indexed by a string. I would never rely on the ordering of components at the same level within the same phase.
  18. Hi Walker, Communicating time values across multiple timescale domains has been a gotcha in Verilog since day one. Timescales only apply to scaling of literal time values, not values of variables or passed arguments. Therefore, you should always use a literal time value in any expression involving time to a normalized time unit. Unfortunately, they didn't do this inside the UVM library. So if your UVM package is compiled with a default of timescale of 1ps, then you should do this to normalize it : uvm_top.set_timeout(2000000ns/1ps, 1); -Dave
  19. You use fork/join_any statements when you want to create a number of time consuming processes and block waiting for one of them to finish. You create two processes, but they do not bloc - the finish immediately because they have fork/join_none statements in them . What you probably meant was something like initial begin me[0] = 1; me[1] = 2; me[2] = 3; repeat(5) begin : repeat_loop fork begin : b1 foreach(me) fork automatic int id = me; print_value (10+id,id); join_none wait fork; end : b1 begin :b2 foreach(me) fork automatic int id = me; print_value (20+id,id); join_none wait fork; end : b2 join_any disable fork; $display(" Disable Fork "); end :repeat_loop $display("@%g Came out of fork-join", $time); #20 $finish; end // initial begin
  20. already answered here:https://verificationacademy.com/forums/systemverilog/use-intersection-cross-coverpoints
  21. The syntax is assert ( randomize(index) with { index inside { [1:5] } ; } ) else begin It's the same {} as if you wrote named constraint block. Each constraint within the {} needs to be terminated with a semi-colon constraint range_constraint { index inside { [1:5] } ; }
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