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dave_59

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Everything posted by dave_59

  1. Hi Linc, Your code works correctly on three other EDAPlayground simulators.
  2. @ljepson74, All you have to do is import uvm_pkg::uvm_enum_wrapper; and you've got this handy little class to use, you don't even need to have a class based testbench.
  3. Verbosity has already been processed before you get to the report catcher. https://accellera.mantishub.io/view.php?id=7211
  4. The UVM field macros do not handle OOP very well, and is one of the many reason we do not recommend using them. It would be much simpler and more efficient to use the streaming operator exactly as you wrote it in a do_pack method.
  5. The link answers the question on how to apply a distribution to any set of constraints. The dist construct only works with explicit values.
  6. https://verificationacademy.com/forums/systemverilog/distributed-weightage-constraint#reply-46525
  7. You always incur overhead for automation. Performance rapidly deteriorates as you introduce dependencies with other random variables. For example, suppose you need 8 unique values between 10 and 20. You are going be calling $urandom_range many extra times throwing away values that don't meet the constraints. And it becomes very difficult to know when there are no solutions, and you end up in infinite loops looking for solutions that are very hard to find or don't exist. This is what a constraint solver does for you. Since constraints are tied to the class inheritance system, they provide
  8. Give your error message a unique ID. Use set_report_severity_id_override to change the severity of that ID from UVM_ERROR to UVM_INFO. Then call get_id_count at the end of your test to make sure it's non-zero.
  9. The return code usually indicates successful completion of the tool and is unrelated to completion of the test. Non-zero return codes would be OS specific error codes. The SystemVerilog standard way of indicating pass/fail status is using the $info/$warning/$error/$fatal messages. Most tools are essentially catch the UVM reports and convert them to one of the SystemVerilog messages. They also have a way of detecting the most severe message issued during a run and you can use that information for determining pass/fail status.
  10. This was recently discussed here. The assertion should fail because disable_assert is false at the start of the attempt.
  11. Works for me in Questa, and in the VCS on edaplayground.com. I mean I get no compilation errors, did not check the functionality of your code. Maybe you are using an older version, Also, I suggest using *.SystemVerilog as file extension of using *.v and -sverilog switch. That helps keep legacy Verilog files working.
  12. I think the problem is with EDAplayground.com appending extra characters at the end of each line. Look carefully at the error messages coming from each tool and you'll see a good explanation of the problem. I believe Aldec is incorrectly ignoring that extra character, so it appears that it is "working".
  13. This works for me in Modelsim/Questa. Note that the newline has been escaped and the resulting string will be displayed as a single line. If you want a newline embedded in the string, you need to add \n.
  14. The syntax is assert ( randomize(index) with { index inside { [1:5] } ; } ) else begin It's the same {} as if you wrote named constraint block. Each constraint within the {} needs to be terminated with a semi-colon constraint range_constraint { index inside { [1:5] } ; }
  15. Questa, like most simulation tools, has a built-in package that will interpret uvm_report_warning as $warning, uvm_report_error as $error, etc. If you do not use that built-in package, then all UVM reports are just simple $display statements. The severity of a failing assertion by default is error, but you can change that by putting a different severity task like $warning in the fail action block. The final TESTSTATUS of a simulation is determined by the most severe message issued during that simulation.
  16. The LRM considers the clocking block output declaration as the assignment to the signal data. The statement cb.data <= value is not a direct assignment to data. Checking this at run-time rather than statically would be a severe performance penalty for all assignments. A modport would not help. You either need to change data to a wire, or conditionally compile/generate the clocking block. Chris Spear is a Synopsys employee and mainly has access to VCS. From my experience with other joint customers, VCS is not performing any assignment checks regardless of whether the clocking block is dri
  17. Questa will also generate an error because the code is illegal as the error message reports. The DUT connection makes a continuous assignment to data, and the clocking block output is consider a procedural assignment to data. Declare data as a wire instead. See http://go.mentor.com/wire-vs-reg for an explanation of why you can;t mix procedural and continuous assignments to the same signal.
  18. You will have to download the UVM kit from the Accellera site and compile it yourself. I don't recall if the student version supports DPI, so you may need to compile it with +define+UVM_NO_DPI
  19. That's not completely correct. The Starter/Student editions will support classes. but not calls to class.randomize(), covergroups, or assertions. So you could create some basic UVM structures.
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