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assert(std::randomize(variable)) when assertions are turned off


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What systemverilog standard defines when we use

assert(std::randomize(variable))

when assertions are turned off

 

I am using it but bit confuse what should simulators do ?

will it still randomize variable

or keep previous value

or it is going to be 0 (variable is int)

 

 

Thanks

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Regardless of the direct answer to your question, I suggest that you not use an immediate assertion to check the result of randomize() and instead use a simple if/else statement. This is because assertions are included the coverage statistics for the design, and this check does not belong with the design, it is part of the testbench. 

 

If you do plan to turn off assertions, I suggest that you apply it to a specific DUT scope instead of globally to the entire simulation. You can also use the new $assertcontrol system task to only target concurrent assertions. Using both these suggestions will ensure that you do not lose the randomize functionality no matter what your tool decides to do.

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Thanks for suggestions, quite useful tips!

But I am still somewhat interested in direct answer,

Assert is IEEE SystemVerilog keyword, standard is loosely defined for this one!

According to my thinking  if assert called inside procedural block it is just used as condition checking statement irrespective of

assertion ON/OFF

And just like function calls simulators should first execute whatever inside inside brackets as arguments before entering into function it self

so randomize() should execute irrespective of assertion ON/OFF and "variable" should have random value

But not sure what different simulators do about this

 

Thanks

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hi,

 

unfortunately its vendor and likely simulator version dependent what happens with (procedural) assert() statements when you use vendor switches to enable/disable assertion execution. as always conditionally enabling/disabling expressions with side-effects via switches and/or commandline is never a sustainable approach.

 

/uwe

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