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Possible bug in uvm_create_random_seed()

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In uvm_create_random_seed() (in uvm_misc.svh) is the following code that returns different seed values for a given {type_id, inst_id}:

  seed_map.seed_table[type_id] = seed_map.seed_table[type_id]+seed_map.count[type_id]; 

  return seed_map.seed_table[type_id];

The problem is that this can return a seed of 0, which is not a valid seed value to srandom().

Am I missing something, or is this really a bug?


Jeff Schroeder

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On 3/12/2022 at 3:27 PM, dave_59 said:

This is a warning from one particular tool, not the UVM code. srandom(seed) is a SystemVerilog language feature and there is no restriction on value of the seed 

Dave, much thanks for your reply!

I have tried, it turns out as you said to be a warning by tools.

My demo code in EDA Playground: pass 0 to process.srandom();

process srandom - EDA Playground

class touseprocess;
   process proc = process::self();
  function procsrandom(int unsigned seed);
    return $urandom;

program test;
  touseprocess up;
  integer x, y, z;
  initial begin
    up = new();
    fork //set a seed at the start of a thread
        x = up.procsrandom(0);
        $display("x = %0d", x);

      //set a seed during a thread
        y = up.procsrandom(200);
        $display("y = %0d", y);

      // draw 2 values from the thread RNG
        z = $urandom + $urandom;
        $display("z = %0d", z);

When i use vcs, i will get the warning, but will not when using other simulators.

Edited by Yesire-Lincoln
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