Jump to content


  • Content Count

  • Joined

  • Last visited

  1. Hii Alan , Thanks for the Reply. Below is the example. property p_period; realtime current_time; disable iff (!nreset) ('1, current_time = $time) |=> (clk_period == ($time - current_time)); endproperty : p_period to display current_time variable in above property ? Regards, Pavan.
  2. Hi , Could you please help me on how to print or display internal variables of property used in sva Regards, Pavan.
  3. Hi Tudor -- Thanks.in generated top address map i commented out those and added other module as submap.
  4. Hi Tudor, when accessing 0x10 .. plan is to access register. thier is no crazy scheme here in top register model ,some address part is left for other internal modules. so these internal modules have thier own register models. so for this internal register models we have to use base address as top model specifies .. Regards, Pavan.
  5. Hi , I have a top register model. in that some address part is defined as memory. ( ex :- 0x0,4,8 ,c registers address then 0x10 memory then 0x20,0x24,0x28 ... registers) I have another register model , which has all the registers which fit the space defined as memory in top register model. (ex: 0x10,0x14,0x18,0x1c as registers) could you please suggest me how to map them . Regards, Pavan.
  6. Hi Guys could you please help me here why questa looping back and forth on above code
  7. Hi Dave -- I have gone through manual and used file break points. I figured out simulator is looping through below code in file :- uvm-1.1d/src/base/uvm_task_phase.svh function:virtual function void execute(uvm_component comp, uvm_phase phase); my concern here is thier is not exactly any loop in this code .but stepping is only looping from top to bottom of below code. // reseed this process for random stability proc = process::self(); proc.srandom(uvm_create_random_seed(phase.get_type_name(), comp.get_full_name())); phase.m_num_procs_not_yet_returned++; if ($cast(seqr,comp)) seqr.start_phase_sequence(phase); exec_task(comp,phase); phase.m_num_procs_not_yet_returned--;
  8. Thanks Dave.could you please help me on how to place break points in existing code.
  9. my simulation got struck at 0ns. how to put break points in code to debug step by step.
  10. I ran a testcase using questa sim,i am getting following output. ** Error: (vsim-3601) Iteration limit reached at time 0 ps testcase run phase look like this. it printed info messages from below code then gave above mentioned error. task run_phase(uvm_phase phase); phase.raise_objection(this); `uvm_info(get_type_name(), "Starting test",UVM_NONE) // generate register settings assert (m_cfg_gen.randomize()) else `uvm_fatal(get_name(),"m_cfg_gen randomization failed"); `uvm_info(get_type_name(), $psprintf("Using this configuration:\n%s",m_cfg_gen.sprint()),UVM_MEDIUM) #20000ns; phase.drop_objection(this); `uvm_info(get_type_name(), "Stopping test...", UVM_LOW ); endtask : run_phase Please help me in resolving this
  • Create New...