Attaluri Posted June 3, 2014 Report Share Posted June 3, 2014 I ran a testcase using questa sim,i am getting following output. ** Error: (vsim-3601) Iteration limit reached at time 0 ps testcase run phase look like this. it printed info messages from below code then gave above mentioned error. task run_phase(uvm_phase phase); phase.raise_objection(this); `uvm_info(get_type_name(), "Starting test",UVM_NONE) // generate register settings assert (m_cfg_gen.randomize()) else `uvm_fatal(get_name(),"m_cfg_gen randomization failed"); `uvm_info(get_type_name(), $psprintf("Using this configuration:\n%s",m_cfg_gen.sprint()),UVM_MEDIUM) #20000ns; phase.drop_objection(this); `uvm_info(get_type_name(), "Stopping test...", UVM_LOW ); endtask : run_phase Please help me in resolving this Quote Link to comment Share on other sites More sharing options...
dave_59 Posted June 3, 2014 Report Share Posted June 3, 2014 You can usually get more verbose help about an error message from Questa by typing verror NNNN In this case type verror 3601. Attaluri 1 Quote Link to comment Share on other sites More sharing options...
Attaluri Posted June 3, 2014 Author Report Share Posted June 3, 2014 my simulation got struck at 0ns. how to put break points in code to debug step by step. Quote Link to comment Share on other sites More sharing options...
Attaluri Posted June 3, 2014 Author Report Share Posted June 3, 2014 Thanks Dave.could you please help me on how to place break points in existing code. Quote Link to comment Share on other sites More sharing options...
dave_59 Posted June 3, 2014 Report Share Posted June 3, 2014 You'll need to look at the Questa User Manual to learn how to set a breakpoint. There are also commands you can use to find out where the simulator was executing at the time of the limit was reached. You might also try increasing the limit to 1000000. Quote Link to comment Share on other sites More sharing options...
Attaluri Posted June 4, 2014 Author Report Share Posted June 4, 2014 Hi Dave -- I have gone through manual and used file break points. I figured out simulator is looping through below code in file :- uvm-1.1d/src/base/uvm_task_phase.svh function:virtual function void execute(uvm_component comp, uvm_phase phase); my concern here is thier is not exactly any loop in this code .but stepping is only looping from top to bottom of below code. // reseed this process for random stability proc = process::self(); proc.srandom(uvm_create_random_seed(phase.get_type_name(), comp.get_full_name())); phase.m_num_procs_not_yet_returned++; if ($cast(seqr,comp)) seqr.start_phase_sequence(phase); exec_task(comp,phase); phase.m_num_procs_not_yet_returned--; Quote Link to comment Share on other sites More sharing options...
Attaluri Posted June 4, 2014 Author Report Share Posted June 4, 2014 Hi Guys could you please help me here why questa looping back and forth on above code Quote Link to comment Share on other sites More sharing options...
tudor.timi Posted June 5, 2014 Report Share Posted June 5, 2014 I'm pretty sure the problem is somewhere else in your code, because that is UVM BCL code. You probably have an endless loop somewhere which is pretty difficult (or better said impossible) to debug on a forum. Quote Link to comment Share on other sites More sharing options...
Recommended Posts
Join the conversation
You can post now and register later. If you have an account, sign in now to post with your account.
Note: Your post will require moderator approval before it will be visible.