Jump to content

UVM (IEEE 1800.2) - Methodology and BCL Forum

Use this forum for posting questions about the UVM (IEEE 1800.2) library and its application to verification environments.

45 topics in this forum

  1. Bit bashing through big endian 32-bit regmodel

    By Bas Arts,
    • 2 replies
    • 627 views

  2. UVM BCL - UVMLint

    By ajeetha,
    • 0 replies
    • 217 views

  3. (Bug?) uvm_reg_map get_size method ignores the n_bytes attribute

    By rtdk,
    • 2 replies
    • 322 views

  4. flush function of uvm_tlm_fifo class does not work as expected

    By JingWang,
    • 2 replies
    • 789 views

  5. uvm_mem_mam currently only supports allocation of <=4G size

    By Atravan,
    • 2 replies
    • 428 views

  6. pack_bytes

    By vennela,
    • 2 replies
    • 388 views

  7. uvm_pkg could not be bound.

    By howard,   
    • 0 replies
    • 544 views

  8. Unified Verification environment for bridges (UVM)

    By Houssam,   
    • 2 replies
    • 458 views

  9. Overlapping field of non conflicting access policy

    By ThomasB,
    • 0 replies
    • 398 views

  10. Checker for write and read data unto register

    By M Prasanth,
    • 0 replies
    • 370 views

  11. Clarification needed on mix between bit bash sequence and single register write

    By Bas Arts,
    • 3 replies
    • 935 views

  12. check while adding multiple fields with same name in same register

    By piyunaffi,
    • 0 replies
    • 291 views

  13. uvm_reg_map::backdoor() issue when using .mirror task

    By yakirp,
    • 0 replies
    • 568 views

  14. No checking for size n and index idx in uvm_vreg.svh

    By kuchen,
    • 1 reply
    • 534 views

  15. Difference between uvm_reg_frontdoor_swq and uvm bit bash sequence

    By spat7172,   
    • 1 reply
    • 570 views

  16. Possible bug in uvm_create_random_seed()

    By jeff.schroeder,
    • 4 replies
    • 1.3k views

  17. 1800.2-2020-2.0 tackling backward compatibility

    By Mark Strickland,
    • 2 replies
    • 780 views

  18. uvm_reg_hw_reset_seq verifying reset value even though has_reset is 0

    By Kasper T,
    • 2 replies
    • 2.3k views

  19. UVM RAL for configuration

    By Amy98,
    • 1 reply
    • 557 views

  20. Removal of runtime phases in future UVM versions

    By Somasekhar,   
    • 1 reply
    • 813 views

  21. Uvm_reg::do_predict() in UVM (1800.2-2020-1.0) does not skip prediction if the status field is set to UVM_NOT_OK

    By salmantanvir,
    • 3 replies
    • 2.2k views

  22. Silent buffer overflow in uvm_packer

    By Rob Donnelly,
    • 2 replies
    • 791 views

  23. Extending uvm_seq_item

    By uvm_learner,
    • 0 replies
    • 624 views

  24. Sideband signals along with DUT Configuration I/F

    By NeerajC,
    • 0 replies
    • 762 views

  25. uvm_reg_hw_reset_seq exclusions appear incorrect

    By Taylor,
    • 1 reply
    • 1.4k views
×
×
  • Create New...