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UVM (IEEE 1800.2) - Methodology and BCL Forum

Use this forum for posting questions about the UVM (IEEE 1800.2) library and its application to verification environments.

46 topics in this forum

  1. Warning-[RT-ISV] Ignoring seed value is triggered due to a bug in function uvm_create_random_seed()

    By Said Soboh,
    • 0 replies
    • 79 views

  2. Bit bashing through big endian 32-bit regmodel

    By Bas Arts,
    • 2 replies
    • 782 views

  3. UVM BCL - UVMLint

    By ajeetha,
    • 0 replies
    • 287 views

  4. (Bug?) uvm_reg_map get_size method ignores the n_bytes attribute

    By rtdk,
    • 2 replies
    • 402 views

  5. flush function of uvm_tlm_fifo class does not work as expected

    By JingWang,
    • 2 replies
    • 873 views

  6. uvm_mem_mam currently only supports allocation of <=4G size

    By Atravan,
    • 2 replies
    • 529 views

  7. pack_bytes

    By vennela,
    • 2 replies
    • 467 views

  8. uvm_pkg could not be bound.

    By howard,   
    • 0 replies
    • 609 views

  9. Unified Verification environment for bridges (UVM)

    By Houssam,   
    • 2 replies
    • 570 views

  10. Overlapping field of non conflicting access policy

    By ThomasB,
    • 0 replies
    • 502 views

  11. Checker for write and read data unto register

    By M Prasanth,
    • 0 replies
    • 442 views

  12. Clarification needed on mix between bit bash sequence and single register write

    By Bas Arts,
    • 3 replies
    • 1.1k views

  13. check while adding multiple fields with same name in same register

    By piyunaffi,
    • 0 replies
    • 334 views

  14. uvm_reg_map::backdoor() issue when using .mirror task

    By yakirp,
    • 0 replies
    • 653 views

  15. No checking for size n and index idx in uvm_vreg.svh

    By kuchen,
    • 1 reply
    • 586 views

  16. Difference between uvm_reg_frontdoor_swq and uvm bit bash sequence

    By spat7172,   
    • 1 reply
    • 624 views

  17. Possible bug in uvm_create_random_seed()

    By jeff.schroeder,
    • 4 replies
    • 1.4k views

  18. 1800.2-2020-2.0 tackling backward compatibility

    By Mark Strickland,
    • 2 replies
    • 837 views

  19. uvm_reg_hw_reset_seq verifying reset value even though has_reset is 0

    By Kasper T,
    • 2 replies
    • 2.5k views

  20. UVM RAL for configuration

    By Amy98,
    • 1 reply
    • 626 views

  21. Removal of runtime phases in future UVM versions

    By Somasekhar,   
    • 1 reply
    • 888 views

  22. Uvm_reg::do_predict() in UVM (1800.2-2020-1.0) does not skip prediction if the status field is set to UVM_NOT_OK

    By salmantanvir,
    • 3 replies
    • 2.3k views

  23. Silent buffer overflow in uvm_packer

    By Rob Donnelly,
    • 2 replies
    • 882 views

  24. Extending uvm_seq_item

    By uvm_learner,
    • 0 replies
    • 668 views

  25. Sideband signals along with DUT Configuration I/F

    By NeerajC,
    • 0 replies
    • 820 views
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