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Bit bashing through big endian 32-bit regmodel

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In `uvm-tests/tests/examples/simple/registers/models/aliasing/`, the register map has been set up using n_bytes = 4 and UVM_BIG_ENDIAN setting. In the test, a bit bashing sequence is is being run. Initially, the bit bashing sequence uses 64-bit data. Hence, the reg2bus function takes as input an object with a 64-bit data field and transforms it into a uvm_sequence_item with a 32-bit data field, to be executed on the bus.

Before the uvm_sequence_item is created, the bytes are reversed (because of UVM_BIG_ENDIAN) through lines 1823-1825 of `uvm_reg_map.svh`:

if ((rw_access.kind == UVM_WRITE) && (endian == UVM_BIG_ENDIAN)) begin
  { >> { rw_access.data }} = { << byte { rw_access.data}};

Due to this, the input data `'h0000000000000001` is translated into `'h0100000000000000`.

The issue is now that the reg2bus function simply ignores the 32 MSB, and therefore, a `0` is written every time.

Can someone from the UVM team confirm that this is correct? (but then, the bit bashing doesn't really make sense in this example)

Or, shouldn't we only reverse the bytes that fit in the bus width (e.g. the 4 LSB)?



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