Kasper T Posted December 14, 2021 Report Share Posted December 14, 2021 I am currently working on a RAL model where some registers do not have any reset value, and actually return X when read the first time after reset. Now, this should be no problem as the has_reset bit is set to 0 on all the fields in these registers, so uvm_reg_hw_reset_seq should not attempt to read them. But it does anyway. And looking into the source code of the sequence, it indeed never checks the has_reset bit. Is this a bug in UVM 1.2? Quote Link to comment Share on other sites More sharing options...
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