Bas Arts Posted December 1, 2022 Report Share Posted December 1, 2022 Consider the following code snippet from uvm-tests/tests/examples/simple/registers/models/aliasing/tb_run.sv: uvm_reg_sequence seq; seq = uvm_reg_bit_bash_seq::type_id::create("seq"); seq.model = env.regmodel; seq.start(env.bus.sqr); seq.wait_for_sequence_state(UVM_FINISHED); `uvm_info("Test", "Verifying aliasing...", UVM_NONE); env.regmodel.Ra.write(status, 32'hDEADBEEF, .parent(seq)); I'm trying to understand a few things here. - the bit bash sequence is in state "UVM_FINISHED" at the moment it is used as a parent sequence for the regmodel register write; should that have a consequence for the write (e.g., the sequence cannot be used anymore because it is finished), or can the register write "reuse" the sequence independent of its state? - what does it actually mean when a regmodel register write is writing a fixed value 32'hDEADBEEF into a register while using a bit bashing sequence as a parent? Is that possible at all? Thanks for giving any clarification on this! Quote Link to comment Share on other sites More sharing options...
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