NeerajC Posted August 17, 2021 Report Share Posted August 17, 2021 For the cases where configuration interfaces have some sideband signals as well along with regular address and data interfaces, what are recommendations as methodology to edit/modify/extend UVM classes. In RAL system, data flows from Sequences to adapter class via model and uvm_reg class functions. RAL model have write/read tasks which comes with an option of extention field which is of type uvm_object. But seemingly there are no option to pass this field to adapter class as adapter class had fixed structure object as argument in reg2bus/bus2reg tasks. What are recommendation in such cases. workaround in driver VIP or there are some means provided as part of UVM base classes. Applications: IPs attached with crossbar. Quote Link to comment Share on other sites More sharing options...
Join the conversation
You can post now and register later. If you have an account, sign in now to post with your account.
Note: Your post will require moderator approval before it will be visible.