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Found 2 results

  1. Hello, I want to develop an unified verification environment for some bridges, so i started by fixing the structure that i want to make : 1) I will have one generic scoreboard, env_top, test, and tb_top 2) The agents of this bridges will be connected in the first time with FIFO, and FIFO will be connected to Scoreboard 3) For having the Coverage, can I have the coverage on the connection between FIFO and Scoreboard ? I want to know if this is right structure to follow ? else i will be gratful to receive other propositions. Thanks,
  2. Below I define a uvm_scoreboard. Why will this not compile when I remove the (3) lines THIS AND THAT? Should it? `uvm_analysis_imp_decl(_rcvd_pkt) //THIS class dpx_rr_scoreboard extends uvm_scoreboard; `uvm_component_utils(dpx_rr_scoreboard) virtual function void write_rcvd_pkt(input some_trans t); //AND THAT endfunction : write_rcvd_pkt //AND THAT endclass : dpx_rr_scoreboard I am using irun 12.X and get the following error when I remove the aforementioned lines: class dpx_rr_scoreboard extends uvm_scoreboard; | ncvlog: *E,FAABP1 (/user/posedgeclk/tb/dpx_rr_scoreboard.svh,25|46): task, function, or assertion instance does not specify all required formal arguments [10.2.2][10\ .3(IEEE)]. I poked around in the uvm class library just a bit, but did not figure this out. Any ideas? Is this a uvm thing or Cadence thing (trying to enforce that I write sensible code) or just fooling thing on my part? I am asking Cadence directly as well, but wanted to throw this out to the crowd. **I am just trying to get a shell of a scoreboard compiling, and don't care that it doesn't do anything yet. Let's ignore the fact that I don't have uvm_analysis_imp_rcvd_pkt created.
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