Jump to content

Toggle Accellera Systems Initiative Accellera Systems Initiative

  Forum Stats Last Post Info


General information from Accellera Systems Initiative

  • 1 topics
  • 0 replies
Welcome! - last post by Admin


Announcements from Accellera Systems Initiative

  • 4 topics
  • 0 replies
Accellera Day at DVCon - Mo... - last post by Admin

In the News

Press Releases and Media Coverage from Accellera Systems Initiative

  • 21 topics
  • 0 replies
Intel's Shishpal Rawat:... - last post by Admin

Toggle IEEE 1735/IP Encryption IEEE 1735/IP Encryption

  Forum Stats Last Post Info


IEEE 1735/IP Encryption general discussion.

  • 3 topics
  • 0 replies
sc_spawn - last post by Pravee


  Forum Stats Last Post Info


IP-XACT general discussion.

  • 16 topics
  • 53 replies
IP-XACT Leon2 example - last post by surfer_dude

Toggle OCP (Open Core Protocol) OCP (Open Core Protocol)

  Forum Stats Last Post Info


OCP general discussion.

  • 3 topics
  • 4 replies
MDatalast signal behaviour... - last post by Scott

Toggle SystemC SystemC

  Forum Stats Last Post Info

SystemC Language

  • 403 topics
  • 1,459 replies
Does ports like sc_in<... - last post by Ralph Görgen

SystemC AMS (Analog/Mixed-Signal)

  • 48 topics
  • 239 replies
How do I stop AMS from inte... - last post by Martin Barnasconi

SystemC TLM (Transaction-level Modeling)

  • 141 topics
  • 398 replies
model with multiple target... - last post by rahuljn

Toggle UVM (Universal Verification Methodology) UVM (Universal Verification Methodology)

  Forum Stats Last Post Info

UVM 1.2 Public Review

Use this forum to provide feedback on the UVM 1.2 release. The review period will end October 1, 2014.

  • 23 topics
  • 57 replies
Dynamic Packed Array - last post by Tudor Timi

Methodology and BCL Forum

Use this forum for posting questions about the UVM library and its application to verification environments.

  • 819 topics
  • 2,557 replies
Configuration of DUT - last post by apfitch

UVM SystemVerilog Discussions

Use this forum when your question is about SystemVerilog language issues in the context of UVM. These can be about how to use a language feature is user code with the UVM or about language usage inside the UVM BCL.

  • 367 topics
  • 916 replies
type_id not in scope when d... - last post by jlnagel

Simulator Specific Issues

Use this forum to discuss tool-specific usage and flow issues.

  • 138 topics
  • 395 replies
SV Constraints Failure due... - last post by apfitch

UVM Commercial Announcements

Use this forum for announcements from UVM ecosystem solution providers including products, demos, videos, training, webinars, etc.

  • 60 topics
  • 47 replies
Learn UVM online! Next onli... - last post by Sumeru_VLSI_training

UVM Surveys

This forum is for the use of the Accellera UVM-WG to ask the UVM community for input. Therefore, all posts will be monitored.

  • 6 topics
  • 1 replies
Runtime synchronization sur... - last post by mbhaduri

Toggle Commercial Announcements Commercial Announcements

  Forum Stats Last Post Info


In this forum, EDA companies may post information about events, videos, training, webinars, and other announcements.

  • 1 topics
  • 0 replies
Mediatek looking for Verifi... - last post by ron76

Recent Topics

  • 8,192 Total Posts
  • 5,536 Total Members
  • abbmir Newest Member
  • 68 Most Online

36 users are online (in the past 15 minutes)

0 members, 36 guests, 0 anonymous users   (See full list)

Google, Bing, Websense