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Lynn Garibaldi

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Lynn Garibaldi last won the day on February 24 2018

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    Elk Grove, CA

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  1. Posting on behalf of Brent Sherman, IPSA WG Chair: Hi Everyone, On behalf of the IP Security Assurance Working Group, I'd like to welcome you to the feedback portal for the SA-EDI 1.0 Public Review. If you haven't yet downloaded the document, it is available here. In order for your voice to be heard, it is imperative that you provide your detailed feedback and questions via this forum before the end of the Public Review period, which will be May 21, 2021. We ask that you make use of the page and line numbers, as well as figure, table, syntax and example numbers/captions to make
  2. Hi everyone, the link in this original post from 2012 has expired as the material is obsolete. Cadence has provided us with a new link to updated videos, which can be found here: https://www.youtube.com/user/CadenceDesign/search?query=SystemVerilog All of the videos at that link are open to the public and most of them are tutorials in the spirit of the original set.
  3. On behalf of the IP Security Assurance (IPSA) Working Group, welcome to the public forum for the IPSA Whitepaper released on September 4th 2019. The Whitepaper details the objectives of the emerging IPSA standard and its approach along with real-case examples highlighting the methodology. We’ve staffed the forum with experts from the IPSA Working Group to answer your questions and bring your suggestions into the committee. We will be analyzing them as part of an effort to release the official IPSA standard. Read or download the Whitepaper here >
  4. The IEEE P1666 (SystemC) Working Group is now operating and looking for new members. If your company is a Corporate IEEE member and you use SystemC for your business, think about joining the P1666 Working Group to make the SystemC standard even better. If you have any questions about joining P1666, please contact Jerome Cornet (jerome.cornet@st.com), IEEE SystemC WG Chair, and Jonathan Goldberg (goldberg.j@ieee.org), IEEE representative for SystemC.
  5. The SystemC Synthesis Working Group is very active and is currently addressing several issues, including: Defining more clearly what elaboration behavior is supported for synthesis. More specifically, the dynamic module instantiation, binding, and naming, (e.g., using loops during elaboration). Considering what array/vector container to support. Looking at the use of C++ 11 attributes for synthesis directives. Analyzing the inclusion of AC datatypes as a numerical library. Our goal over the next 12 months is to see some convergence on a second version of the SystemC
  6. The Accellera Board of Directors has approved Portable Test and Stimulus 1.0 as an Accellera standard. The Portable Test and Stimulus Standard (PSS) defines a specification to create a single representation of stimulus and test scenarios usable by a variety of users across many levels of integration under different configurations. This representation facilitates the generation of diverse implementations of a scenario that run on a variety of execution platforms, including, but not necessarily limited to, simulation, emulation, FPGA prototyping, and post-silicon. With this standard, users can s
  7. The Accellera UVM Working Group has released the UVM 2017 0.9 reference implementation. This implementation is available as a SystemVerilog class library and is fully compatible with the IEEE 1800.2-2017 standard as defined in the Language Reference Manual. The library can be downloaded for free here. The IEEE 1800.2-2017 standard is available free of charge from the IEEE Get program, courtesy of Accellera. We encourage you to use this forum to provide feedback, ask questions, and engage in discussions.
  8. UVM-SystemC 1.0-beta1 has been released for public review. This update contains compatibility updates to SystemC 2.3.2 and newer compiler versions. It also has a HDL path API implementation, update finish on completion mechanism, an updated LRM, UVM backdoor for SystemC dummy registers uvm_sc_reg, and aligned reporting API with UVM 1.2. Download it here >. The review will remain open until February 7, 2018. Feedback is welcome and can be posted here on this Community Forum.
  9. The Accellera SystemC Language Working Group has released the proposed SystemC 2.3.2 for testing and feedback from the community. This is a maintenance release with some new features including a foundation for C++11/14 enablement, a centralized global name registration enabling CCI naming requirements, new TLM socket and sc_signal base classes, and updated compiler and platform support including Windows DLL support and an experimental CMake build system. There are also many bug-fixes and general clean-up. Licensed under Apache 2.0, the release package contains the SystemC class library and the
  10. The first SystemC Evolution Day was a huge success! Check out the wrap-up and download the presentations.
  11. The SystemC Evolution Day is a new, full-day technical workshop on the evolution of SystemC standards to advance the SystemC ecosystem. It will be held on Tuesday, May 3, 2016 in Munich, Germany. In several in-depth sessions, selected current and future standardization topics around SystemC will be discussed in order to accelerate their progress for Accellera/IEEE standard’s inclusion. The new SystemC Evolution Day is intended as a lean, user-centric, hands-on forum bringing together the experts from the SystemC user community and the Accellera Working Groups to advance the SystemC standa
  12. The 2016 Call for Papers and Call for Tutorials are now live! Paper Submissions will open March 15, and Tutorial Submissions will open on March 22. Travel info and program can be found at www.dvcon-europe.org.
  13. DVCon India 2016 September 15 - 16, 2016 The Leela Palace, Bangalore, India Call for Abstracts Submission Deadline: May 17, 2016 Call for Tutorials Submit proposals by May 17, 2016 www.dvcon-india.org
  14. The SystemC Verification Working Group (VWG) has made available an early UVM-SystemC Language Reference Manual (LRM) accompanied by a Proof-of-Concept (PoC) implementation for public review. The purpose of this public review is to obtain feedback on the LRM and PoC distribution. The working group is looking for discrepancies versus the standard and simple install/documentation issues against the supported platforms. For details, FAQ and to download the library please visit the VWG page on the Accellera web site.
  15. To view this announcement on the IEEE web site click here. Purpose Verification components and environments are currently created in different forms, making interoperability among verification tools and/or geographically-dispersed design environments both time consuming to develop and error prone. The results of the UVM standardization effort will improve interoperability and reduce the cost of repurchasing and rewriting Intellectual Property (IP) for each new project or electronic design automation tool, as well as make it easier to reuse verification components. Overall, the UVM standar
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