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Lynn Garibaldi

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Lynn Garibaldi last won the day on February 24 2018

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    Elk Grove, CA

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  1. Hi everyone, the link in this original post from 2012 has expired as the material is obsolete. Cadence has provided us with a new link to updated videos, which can be found here: https://www.youtube.com/user/CadenceDesign/search?query=SystemVerilog All of the videos at that link are open to the public and most of them are tutorials in the spirit of the original set.
  2. On behalf of the IP Security Assurance (IPSA) Working Group, welcome to the public forum for the IPSA Whitepaper released on September 4th 2019. The Whitepaper details the objectives of the emerging IPSA standard and its approach along with real-case examples highlighting the methodology. We’ve staffed the forum with experts from the IPSA Working Group to answer your questions and bring your suggestions into the committee. We will be analyzing them as part of an effort to release the official IPSA standard. Read or download the Whitepaper here >
  3. The IEEE P1666 (SystemC) Working Group is now operating and looking for new members. If your company is a Corporate IEEE member and you use SystemC for your business, think about joining the P1666 Working Group to make the SystemC standard even better. If you have any questions about joining P1666, please contact Jerome Cornet (jerome.cornet@st.com), IEEE SystemC WG Chair, and Jonathan Goldberg (goldberg.j@ieee.org), IEEE representative for SystemC.
  4. The SystemC Synthesis Working Group is very active and is currently addressing several issues, including: Defining more clearly what elaboration behavior is supported for synthesis. More specifically, the dynamic module instantiation, binding, and naming, (e.g., using loops during elaboration). Considering what array/vector container to support. Looking at the use of C++ 11 attributes for synthesis directives. Analyzing the inclusion of AC datatypes as a numerical library. Our goal over the next 12 months is to see some convergence on a second version of the SystemC Synthesis standard with the issues resolved and based on more updated versions of the C++ standard such as C++ 11, 14, and possibly 17. At SystemC Evolution Day last October there were some datatype proposals presented (download using links below), and we’d like to get more feedback from the community on them. Suggestions and input are welcome in this forum. We look forward to hearing from you. SystemC Datatypes Proposal Algorithmic Datatypes Proposal
  5. The Accellera Board of Directors has approved Portable Test and Stimulus 1.0 as an Accellera standard. The Portable Test and Stimulus Standard (PSS) defines a specification to create a single representation of stimulus and test scenarios usable by a variety of users across many levels of integration under different configurations. This representation facilitates the generation of diverse implementations of a scenario that run on a variety of execution platforms, including, but not necessarily limited to, simulation, emulation, FPGA prototyping, and post-silicon. With this standard, users can specify a set of behaviors once and observe consistent behavior across multiple implementations. The new standard is available immediately to download for free. Release notes stating the differences between the Early Adopter II Release to the 1.0 standard are available. For more information, a press release and supporting industry quotes are also available. Accellera’s Portable Stimulus Community is also a resource for the latest information available on the new standard.
  6. The Accellera UVM Working Group has released the UVM 2017 0.9 reference implementation. This implementation is available as a SystemVerilog class library and is fully compatible with the IEEE 1800.2-2017 standard as defined in the Language Reference Manual. The library can be downloaded for free here. The IEEE 1800.2-2017 standard is available free of charge from the IEEE Get program, courtesy of Accellera. We encourage you to use this forum to provide feedback, ask questions, and engage in discussions.
  7. Please note the review period ended March 30, 2018. The Accellera Portable Stimulus Working Group (PSWG) is proud to announce the release for public review of the latest preliminary version of the Portable Test and Stimulus Standard. This Early Adopter II release includes additional work done by the PSWG since the release in June 2017 of the first Early Adopter version, reflecting progress on a wide range of issues to improve the standard, including user feedback on the EA version. The PSWG continues to work to ensure a robust, feature-rich release which will enable users and vendors to benefit from the powerful productivity-increasing technology with the confidence that comes from using an approved Accellera Standard. The Portable Test and Stimulus Standard defines a domain-specific language (DSL) and an accompanying semantically-equivalent C++ library to create a single representation of stimulus and test scenarios, usable by a variety of users across different levels of integration under different configurations. It will permit the generation of multiple scenarios from a single specification of test intent and allow tools to create different implementations of a scenario that run on a variety of execution platforms, including, but not limited to, simulation, emulation, FPGA prototyping, post-silicon and virtual platforms. With this standard, users can specify a set of behaviors once, from which multiple implementations may be derived. The Portable Test and Stimulus Standard is still a work in progress. We invite further public review and comment on the Early Adopter II release to help move us closer to our goal of an approved 1.0 standard. The standard includes features to allow: Abstract behavioral specification and scheduling Data structures, constrained randomization and data flow modeling Scenario-level randomization from abstract partial specifications to preserve critical intent Encapsulation, composition and reuse of modeling components With this standard, users can specify a set of behaviors once and observe consistent behavior across multiple implementations. For more information on the Portable Test and Stimulus Standard download the tutorial, “Portable Test and Stimulus: The Next Level of Verification Productivity is Here.” Members of the Working Group presented the tutorial at DVCon U.S. on Monday, February 26, 2018. The Public Review Period will be open until Friday, March 30, 2018. Please provide your feedback, ask questions and interact on issues regarding the Early Adopter II release via the Accellera Portable Stimulus Forum. All comments will be reviewed by the PSWG. Download the Portable Stimulus Standard Early Adopter II release >
  8. UVM-SystemC 1.0-beta1 has been released for public review. This update contains compatibility updates to SystemC 2.3.2 and newer compiler versions. It also has a HDL path API implementation, update finish on completion mechanism, an updated LRM, UVM backdoor for SystemC dummy registers uvm_sc_reg, and aligned reporting API with UVM 1.2. Download it here >. The review will remain open until February 7, 2018. Feedback is welcome and can be posted here on this Community Forum.
  9. The Accellera SystemC Language Working Group has released the proposed SystemC 2.3.2 for testing and feedback from the community. This is a maintenance release with some new features including a foundation for C++11/14 enablement, a centralized global name registration enabling CCI naming requirements, new TLM socket and sc_signal base classes, and updated compiler and platform support including Windows DLL support and an experimental CMake build system. There are also many bug-fixes and general clean-up. Licensed under Apache 2.0, the release package contains the SystemC class library and the regression test suite. It can be downloaded here. The review period is open until May 31, 2017. Feedback is welcome and can be submitted either by email to review-systemc@lists.accellera.org or via this forum.
  10. The first SystemC Evolution Day was a huge success! Check out the wrap-up and download the presentations.
  11. The SystemC Evolution Day is a new, full-day technical workshop on the evolution of SystemC standards to advance the SystemC ecosystem. It will be held on Tuesday, May 3, 2016 in Munich, Germany. In several in-depth sessions, selected current and future standardization topics around SystemC will be discussed in order to accelerate their progress for Accellera/IEEE standard’s inclusion. The new SystemC Evolution Day is intended as a lean, user-centric, hands-on forum bringing together the experts from the SystemC user community and the Accellera Working Groups to advance the SystemC standards in a full day workshop. View complete details and register >
  12. The 2016 Call for Papers and Call for Tutorials are now live! Paper Submissions will open March 15, and Tutorial Submissions will open on March 22. Travel info and program can be found at www.dvcon-europe.org.
  13. DVCon India 2016 September 15 - 16, 2016 The Leela Palace, Bangalore, India Call for Abstracts Submission Deadline: May 17, 2016 Call for Tutorials Submit proposals by May 17, 2016 www.dvcon-india.org
  14. The SystemC Verification Working Group (VWG) has made available an early UVM-SystemC Language Reference Manual (LRM) accompanied by a Proof-of-Concept (PoC) implementation for public review. The purpose of this public review is to obtain feedback on the LRM and PoC distribution. The working group is looking for discrepancies versus the standard and simple install/documentation issues against the supported platforms. For details, FAQ and to download the library please visit the VWG page on the Accellera web site.
  15. To view this announcement on the IEEE web site click here. Purpose Verification components and environments are currently created in different forms, making interoperability among verification tools and/or geographically-dispersed design environments both time consuming to develop and error prone. The results of the UVM standardization effort will improve interoperability and reduce the cost of repurchasing and rewriting Intellectual Property (IP) for each new project or electronic design automation tool, as well as make it easier to reuse verification components. Overall, the UVM standardization effort will lower verification costs and improve design quality throughout the industry. Need for the Project As the electronics industry builds more complex systems involving large numbers of components, the challenge of verifying such systems multiplies by orders of magnitude. In order to bring costs and time to market down, standardization must happen to enable as much modularity and reuse across verification components as possible. The UVM standard will propagate an API that will manage this explosion in verification complexity, allowing the entire industry to write and reuse verification components both (a) internally in companies having geographically widespread teams, and (externally between vendors and user companies in the electronics industry, who are developing, selling and using verification components Call for Contribution Please review the IEEE P1800.2 ™ PAR and, if you are interested in participating, Register for the first working group meeting scheduled to occur on August 6th, 2015 from 12pm – 2pm Eastern Daylight Time (EDT) / 9am – 11am Pacific Daylight Time (PDT). Please feel free to connect with the Working Group Chair, Thomas Alsop at thomas.r.alsop@intel.com or IEEE-SA staff Jonathan Goldberg at goldberg.j@ieee.org directly for further information.
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