Lynn Garibaldi Posted February 7 Report Share Posted February 7 Accellera has formed a new Mixed Signal Interface Working Group to continue and standardize the work that was started under IEEE 1800-2023, to support bidirectional net connections between logic/UDN and analog/electrical/real signals in SystemVerilog. Since that work was not completed for 1800-2023, the quickest way to standardize that work is through Accellera. You are cordially invited to participate in this new Working Group to help us complete this important work. Many of you will have seen the work-in-progress proposal that was started in the P1800 AMS Subgroup, as that group shared their proposal with P1800, UVM-MS and SystemVerilog-AMS at meetings a few months ago. The goal of the MSI WG is to complete that work and issue a standard as an update to 1800-2023. We would like to start meeting as a Working Group around mid-March. Meetings will likely be for 1 hour every week or every other week, depending on participants’ schedules. Please reply to this email and let me know if you are interested in participating. Since this is an Accellera Working Group, your company will need to be an Accellera member to participate. If your company is not an Accellera member, we can help you become one. Thank you for considering being a part of the MSI-WG. Warmest regards, -Tom Fitzpatrick Accellera Announces SystemVerilog MSI WG FINAL for 02.07.24.docx Link to comment Share on other sites More sharing options...
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