acc_sysC

Below is a snippet of the stimulus I am giving to my design. I want all of the assignments to be non-blocking and so I have declared everything as sc_signal. However, the problem arises with the need to use range() Here ACC, B and Y use range(). Since range() cannot be used with sc_signal, I used a copy of them as a sc_bv. I think because of this, the statements are becoming blocking assignments in between and these signals are always 0 in my waveform. Please suggest ways to deal with this problem. sc_signal<sc_bv<M> >A; sc_signal<sc_bv<M> >B; sc_signal<sc_bv<1<<M> > FUNC; constexpr static int size = ceil(log2(M)); sc_signal<sc_uint<size> > FUNC_ADDR; sc_signal<sc_bv<N> > LOAD_CORE; constexpr static int size_addr = ceil(log2(2*(N-1))); sc_signal<sc_bv<N*size_addr> > AIN_ADDR; sc_signal<sc_bv<N*size_addr> > BIN_ADDR; sc_signal<sc_bv<2*N> > SRC_MODE; sc_signal<sc_bv<2*N> > IN_MODE; sc_signal<sc_bv<N> > RUN; //sc_clock clk("clock", 6, SC_NS); //sc_signal<bool> clk; sc_in_clk clk; sc_signal<bool> reset; constexpr static int size_y_addr = ceil(log2(N)); sc_signal<sc_bv<size_y_addr> > Y_ADDR; sc_signal<sc_bv<M> > Y; sc_signal <sc_bv<16> > Accumulator; sc_bv<M>Y_copy; sc_bv<16> ACC = 0; sc_bv<M> B_copy; * * * CODE * * * wait(clk.posedge_event());//1 A.write(36); B.write(129); IN_MODE.write(0x3FC00); SRC_MODE.write(0x3FC00); AIN_ADDR.write(0x223300000); BIN_ADDR.write(0x010100000); wait(clk.posedge_event());//2 //wait(6,SC_NS); B_copy = B.read(); B_copy.range(3,0) = ACC.range(3,0); B.write(B_copy); IN_MODE.write(0x00333); SRC_MODE.write(0x00001); AIN_ADDR.write(0x0B0C00); BIN_ADDR.write(0xD0F0E); RUN.write(0x1E0); wait(clk.posedge_event());//3 Y_copy = Y.read(); B_copy.range(3,0) = ACC.range(7,4); B.write(B_copy); IN_MODE.write(0x003BB); SRC_MODE.write(0x00113); AIN_ADDR.write(0x80800); BIN_ADDR.write(0x87A38); RUN.write(0x015); wait(clk.posedge_event());//4 B_copy.range(3,0) = ACC.range(11,8); B.write(B_copy); IN_MODE.write(0x00357); SRC_MODE.write(0x00201); AIN_ADDR.write(0x17638); BIN_ADDR.write(0x00002); RUN.write(0x015); Y_ADDR.write(0x0000); wait(clk.posedge_event());//5 Y_copy = Y.read(); ACC.range(7,4) = Y_copy.range(3,0); Accumulator.write(ACC); B_copy.range(3,0) = ACC.range(15,12); B.write(B_copy); IN_MODE.write(0x003E3); SRC_MODE.write(0x00342); AIN_ADDR.write(0x08006); BIN_ADDR.write(0x89208); RUN.write(0x01B); wait(clk.posedge_event());//6 IN_MODE.write(0x00333); SRC_MODE.write(0x00121); AIN_ADDR.write(0x80408); BIN_ADDR.write(0x10802); RUN.write(0x01D); wait(clk.posedge_event()); //7 ACC.range(11,8) = Y_copy.range(3,0); Accumulator.write(ACC); IN_MODE.write(0x0000B); SRC_MODE.write(0x00002); AIN_ADDR.write(0x00006); BIN_ADDR.write(0x00028); RUN.write(0x015); wait(clk.posedge_event());//8 IN_MODE.write(0x00004); SRC_MODE.write(0x00000); AIN_ADDR.write(0x00000); BIN_ADDR.write(0x00000); RUN.write(0x001); Y_ADDR.write(0x0001); wait(clk.posedge_event());//9 ACC.range(15,12) = Y_copy.range(3,0); Accumulator.write(ACC); IN_MODE.write(0x00000); RUN.write(0x002); wait(clk.posedge_event());//10 Y_ADDR.write(0x0000); IN_MODE.write(0x00000); RUN.write(0x000);

Thanks David! That helped me understand where I'm going wrong. But I'm a little confused as to how to implement this in the structure of code I'm using. I will used an example which is similar to my situation here: https://edaplayground.com/x/JaQu If I declare everything in my stimulus.h file as sc_signal, it gives error like this when I connect it in my main file(register_main.cpp): register_main.cpp:37:23: error: no match for call to '(sc_core::sc_signal<sc_dt::sc_bv<256> >) (sc_core::sc_signal<sc_dt::sc_bv<256> >&)'stim1.Data_in(DATA_IN); which makes sense because of data type conflicts. So does this mean I should be implementing the syntax you suggested directly in my main file(register_main.cpp)? How do I do this if I want to keep the stimulus in a separate headerfile and then just connect the signals in the main file? Please advice.

How do I write the below testbench which has non-blocking assignments in systemC? The entire model in systemC is written using SC_METHODs I tried to write the below testbench(stimulus) using SC_THREAD since I could use wait(clk.posedge_event()) in place of @(posedge clk) I am able to see the stimulus correctly same as RTL in the waveforms from VCD file. But will this work same as non-blocking assignment in verilog. I have this question because I know non-blocking assignment in systemC can be done using SC_METHOD(). Please find the systemC code I wrote in the attachment Please advice. module test; reg [8-1 : 0] A; reg [8-1 : 0] B; reg [256-1 : 0] FUNC; reg [8-1 : 0] FUNC_ADDR; reg [9-1 : 0] RUN; reg [9-1 : 0] LOAD_CORE; reg [18-1 : 0] SRC_MODE; reg [18-1 : 0] IN_MODE; reg [36-1 : 0] AIN_ADDR; reg [36-1 : 0] BIN_ADDR; reg [4-1 : 0] Y_ADDR; reg clk; reg reset; wire [8-1 : 0] Y; PIM_Cluster top( .A(A), .B(B), .FUNC(FUNC), .FUNC_ADDR(FUNC_ADDR), .RUN(RUN), .LOAD_CORE(LOAD_CORE), .SRC_MODE(SRC_MODE), .IN_MODE(IN_MODE), .AIN_ADDR(AIN_ADDR), .BIN_ADDR(BIN_ADDR), .Y_ADDR(Y_ADDR), .clk(clk), .reset(reset), .Y(Y) ); integer n = 16; integer index = 0; integer a = 0; integer b = 0; integer kk = 0; integer qq =0; integer ii = 0; integer add = 0; integer mult = 0; reg [2048-1:0] FUNC_MULT; reg [2048-1:0] FUNC_ADD; reg [8-1:0] ADD_tmp; reg [8-1:0] MULT_tmp; reg [16-1:0] ACC; genvar G; initial begin $timeformat(-9,2,"ns", 16); `ifdef SDFSCAN $sdf_annotate("sdf/PIM_Cluster_tsmc18_scan.sdf", test.top); `endif // Initialize Inputs ACC = 16'h0; A = 8'h0; B = 8'h0; FUNC = 256'h0; FUNC_ADDR = 9'h0; RUN = 9'h1FF; LOAD_CORE = 9'h0; SRC_MODE = 18'h0; IN_MODE = 18'h0;//h3ffff AIN_ADDR = 36'h0; BIN_ADDR = 36'h0; Y_ADDR = 4'h0; clk = 0; reset = 0; //Generate Function Words for Multiplication and Addition for (a=0;a<16;a=a+1) begin - - - - - end index = index + 1; end end #5; reset = 1; #5; reset = 0; //LOAD_CORE = 9'h0; for (ii=0;ii<n;ii=ii+1) begin // @(posedge clk) // begin // A <= $random%256; // B <= $random%256; // end @(posedge clk) //#6; A <= $random%256; B <= $random%256; IN_MODE <= 18'h3FC00; SRC_MODE <= 18'h3FC00; AIN_ADDR <= {16'h2233,20'h0}; BIN_ADDR <= {16'h0101,20'h0}; //repeat(2) @(posedge clk); //#6; //A = 0; //B = 0; B[3:0] <= ACC[3:0]; IN_MODE <= 18'h00333; SRC_MODE <=18'h00001; AIN_ADDR <= {16'h0,20'h0B0C00}; BIN_ADDR <= {16'h0,20'h0D0F0E}; RUN <= 9'h1E0; //repeat (3) @(posedge clk); //#6; ACC[3:0] <= Y[3:0]; B[3:0]<= ACC[7:4]; IN_MODE <= 18'h003BB; SRC_MODE <= 18'h00113; AIN_ADDR <= {16'h0,20'h80800}; BIN_ADDR <= {16'h0,20'h87A38}; RUN<= 9'h015; //repeat (4) @(posedge clk);//4 //#6; B[3:0] <=ACC[11:8]; IN_MODE <=18'h00357; SRC_MODE <=18'h00201; AIN_ADDR<= {16'h0,20'h17638}; BIN_ADDR<= {16'h0,20'h00002}; RUN <=9'h015; Y_ADDR <=4'h0000; //repeat (5) @(posedge clk); //#6; ACC[7:4] <=Y[3:0]; B[3:0]<= ACC[15:12]; IN_MODE <=18'h003E3; SRC_MODE<= 18'h00342; AIN_ADDR <= {16'h0,20'h08006}; BIN_ADDR <= {16'h0,20'h89208}; RUN <= 9'h01B; //repeat (6) @(posedge clk); //#6; IN_MODE <= 18'h00333; SRC_MODE <= 18'h00121; AIN_ADDR <= {16'h0,20'h80408}; BIN_ADDR <= {16'h0,20'h10802}; RUN <= 9'h01D; //repeat (7) @(posedge clk); //#6; ACC[11:8] <= Y[3:0]; IN_MODE <= 18'h0000B; SRC_MODE <= 18'h00002; AIN_ADDR<= {16'h0,20'h00006}; BIN_ADDR <={16'h0,20'h00028}; RUN <=9'h015; //repeat (8) @(posedge clk); //#6; IN_MODE <= 18'h00004; SRC_MODE <= 18'h00000; AIN_ADDR <= {16'h0,20'h00000}; BIN_ADDR <= {16'h0,20'h00000}; RUN<= 9'h001; Y_ADDR <= 4'h0001; //repeat (9) @(posedge clk); //#6; ACC[15:12] <= Y[3:0]; IN_MODE <= 18'h00000; RUN <= 9'h002; @(posedge clk); //#6; Y_ADDR <= 4'h0000; IN_MODE <= 18'h00000; RUN <= 9'h000; end $stop; end always #3 clk = ~clk; endmodule PIMC_stimulus (1).h

Figured out a way shown below. But is there any other better solution to this? B_copy = B.read(); B_copy.range(3,0) = ACC.range(3,0); B.write(B_copy);

Verilog code: reg [7:0] B; reg [15:0] ACC; B[3:0] = ACC[3:0]; Equivalent systemC code: This module is a stimulus module so I am declaring B as output port sc_out<sc_bv<8> > B; sc_bv<8> B_copy; sc_bv<16> ACC; B_copy.range(3,0) = ACC.range(3:0); This is what I want to do but its not possible because range() cannot be used with ports. How should this be done in systemC? B.range(3,0).write(B_copy); I also don't want bits 4,5,6,7, to be overwritten with 0s Please advice

@Eyck Yes I missed the "public". I have it in all my other modules but missed it in this my bad. Thanks.

Following is the complete error message: In file included from /classes/eeee720/systemc/systemc-2.3.3/include/systemc:118:0, from /classes/eeee720/systemc/systemc-2.3.3/include/systemc.h:219, from PIMC_main.cpp:2: /classes/eeee720/systemc/systemc-2.3.3/include/sysc/utils/sc_vector.h: In instantiation of 'sc_core::sc_object* sc_core::sc_vector<T>::object_cast(void*) const [with T = In_multiplexer<9, 4>]': PIMC_main.cpp:87:1: required from here /classes/eeee720/systemc/systemc-2.3.3/include/sysc/utils/sc_vector.h:508:59: error: 'sc_core::sc_object' is an inaccessible base of 'In_multiplexer<9, 4>' { return implicit_cast( static_cast<element_type*>(p) ); } ^ /classes/eeee720/systemc/systemc-2.3.3/include/sysc/utils/sc_vector.h: In member function 'sc_core::sc_object* sc_core::sc_vector<T>::object_cast(void*) const [with T = In_multiplexer<9, 4>]': /classes/eeee720/systemc/systemc-2.3.3/include/sysc/utils/sc_vector.h:508:62: warning: control reaches end of non-void function [-Wreturn-type] { return implicit_cast( static_cast<element_type*>(p) ); } Can anyone please help me understand this error message? I have no idea where to begin solving this. Because of this line /classes/eeee720/systemc/systemc-2.3.3/include/sysc/utils/sc_vector.h: In member function 'sc_core::sc_object* sc_core::sc_vector<T>::object_cast(void*) const [with T = In_multiplexer<9, 4>]': I thinks it has do with the vector of type In_multiplexer. I am using In_multiplexer as a single object and as a vector of objects. But it does not complain about the former. Here is how I declared them and used them: N = 9, M =8 SINGLE OBJECT: In_multiplexer<N,M/2> AMux0{"AMux0"}; AMux0.A(A); AMux0.B(B); AMux0.MODE(AMux0_SRC); AMux0.CORES(AMux0_sY); AMux0.SEL(AMux0_AIN_ADDR_part_select); AMux0.Y(pimcore0_A_part_select); VECTOR OF OBJECTS: sc_vector<In_multiplexer<N,M/2>> AMux{"AMux", N-2}; for (auto G = 1; G<N-1; ++G) { AMux[G].A(A); AMux[G].B(B); AMux[G].MODE(AMux_mode_vec[G]); AMux[G].CORES(AMux_core_vec[G]); AMux[G].SEL(AMux_sel_vec[G]); AMux[G].Y(part_sA[G]); }

@Eyckit works now! Thanks

@Eyck it still gives me only 0s. Is it giving you some value when Data_in is printed out? I'm not sure if I am doing something wrong. The output as seen here:https://www.edaplayground.com/x/Dr6L

I tried the following ways: auto write_val = sc_dt::sc_biguint<64>(0xffffffffffffffff)<<192 + sc_dt::sc_biguint<64>(0xffffffffffffffff)<<128 + sc_dt::sc_biguint<64>(0xffffffffffffffff)<<64 + sc_dt::sc_biguint<64>(0xffffffffffffffff); Also tried this: sc_dt::sc_biguint<N> write_val = sc_dt::sc_biguint<64>(0xffffffffffffffff)<<192 + sc_dt::sc_biguint<64>(0xffffffffffffffff)<<128 + sc_dt::sc_biguint<64>(0xffffffffffffffff)<<64 + sc_dt::sc_biguint<64>(0xffffffffffffffff); It compiles but does not take any values I give it. write_val always has 0s. Please guide me. EDA link:https://www.edaplayground.com/x/Dr6L

@maehne I tried this but it looks like its not taking any values I give. When I print it out it gives only 0s https://www.edaplayground.com/x/Dr6L

@Eyck I tried it and it gives me this error: error: expected primary-expression before ':' token auto write_val = sc_dt:.sc_biguint<64>(0x2238787)<<192 + sc_dt:.sc_biguint<64>(0xf909278327848273)<<128 + sc_dt:.sc_biguint<64>(0x46738ffff)<<64 + sc_dt:.sc_biguint<64>(0xffffffffff130389); Here's the EDA link:https://www.edaplayground.com/x/bUPa

Is there any data type bigger than sc_biguint ?? I want to give an input of 256 bits. It throws errors even after using sc_biguint/sc_bv. Please suggest what can be done.

That makes a lot of sense! It worked. Thanks!

Gotcha! Thanks