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Found 4 results

  1. Hello, To debug the bindings between various signals, ports and interfaces connections, is there a way to display the binding information? Consider the following example: // https://www.edaplayground.com/x/JZsM #include <systemc> using namespace sc_core; SC_MODULE(InternalCounter) { sc_in_clk clock{"clock"}; sc_in<bool> enable{"enable"}; SC_CTOR(InternalCounter){}; }; SC_MODULE (Counter) { sc_in_clk clock{"clock"}; sc_in<bool> reset{"reset"}; sc_in<bool> enable{"enable"}; InternalCounter ic{"ic"}; SC_CTOR(Counter){ ic.clock(clock); ic.enable(enable); } }; SC_MODULE (CounterDriver) { sc_clock clk_s {"clk_s"}; sc_out<bool> reset{"reset"}; sc_out<bool> enable{"enable"}; SC_CTOR(CounterDriver){} }; SC_MODULE(Top) { sc_signal<bool, SC_MANY_WRITERS> reset_s{"reset_s"}; sc_signal<bool> enable_s{"enable_s"}; Counter c {"c"}; CounterDriver cd{"cd"}; SC_CTOR(Top) { c.clock(cd.clk_s); c.reset(reset_s); cd.reset(reset_s); c.enable(enable_s); cd.enable(enable_s); } }; int sc_main(int argc, char**argv) { Top top("top"); sc_start(1, SC_NS); // print_connectivity(top); return 0; } What I would want is a function like print_connectivity below which prints the following. Signal Connectivity top.cd.clk_s:: top.c.clock -> top.c.ic.clock top.reset_s:: top.cd.reset -> top.c.reset top.enable_s:: top.cd.enable -> top.c.enable -> top.c.ic.enable
  2. Hi, I am dynamically populating a network of SC_MODULES inside a global modele `net`. As soon as I create a module `x`, I bind all ports to x (say `a` and `b`) to `sc_signal` x.a and x.b in `net`. When I simulate, all SC_MODULEs run independently and I can see values of `sc_signal`s changing when port value changes. So far so good! This has the advantage and end-user does not have to bind all the ports (many of them are really not essential). Now I wish to connect port `a` and `b` of module `x` to port of `m` and `n` of module `y`. Any new binding will raise an error since I am allowing maximum of 1 binding. I can change the number of binding to 2 but I am not sure if it will cost me run time penalty. If penalty is not significant I can go with this. Anyway I was wordering, how can delete the previous binding on port `m` and `n`? Deleting the signal `y.m` and `y.n` is sufficient? If it is not possible, I'll think of something else.
  3. I am looking for a table that summarizes what port binds to what. specifically binding simple_initiator_socket_tagged to simple_target_socket and vice versa. Thanks
  4. Hi all, I created two modules with interfaces as below: M1 : sc_port<sc_fifo_out_if<T>, 0> a M2 : sc_port<sc_fifo_in_if<T>, 0> a2; I have a third module which is also my top module i.e M3 and tried binding M1 output to M2 input to create a communication channel. I have tried using sc_fifo<T> but it doesn't work. How do I bind M1 output to M2 input inside M3 module? Please not that T is a struct. Thanks
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