How to do this port declaration in systemC? Verilog declaration: input [$clog2(N)-1] X;

[acc_sysC]

I tried using ceil() but it doesn't work.

Please guide me.

[karthickg]

I can guess what you are trying - but please post the complete question and the code you are trying. That way, the responses here are more meaningful for those who search the forum later.

The easiest and most general way to create an array of ports is to use `sc_vector` construct in SystemC. E.g.

class my_module : public sc_module
{
   public:
      sc_vector<sc_in<bool>> in_port;
      my_module(sc_module_name n, int sz) : sc_module(n), in_port("in_port", sz) { ... }
};

 

[David Black]

How is N declared?

Also, you need to keep the distinctions of compile-time, elaboration-time and run-time distinct in your thinking. Template parameters and array size declarators all require compile-time constants. In turn these can be dealt with computationally but only if using constexpr functions. Depending on the version of C++ and your library implementation, you might be having issues. 
 

Yor problems are all C++ syntax and very little to do with SystenC itself. 

[acc_sysC]

It is true. I am learning C++ and systemC. Both are new to me. Thanks for pointing out that these are more C++ problems. I will refer to C++ materials from now on.

Coming to the solution, for the people who search the forum later, this is what I did after taking your suggestions:

constexpr static int select_size = ceil(log2(1<<N));

and passed select_size as a parameter to a templated module and it works.

Thanks for your suggestions @David Black and @karthickg