Is it possible to integrate UVM-SystemC and UVM-ML in the same testbench environment?

[tyee]

Hello,

  I'm trying to use UVM-SystemC and UVM-ML within the same environment. My goal is to run a UVM-SystemC testbench to simulate the C model (without using VCS) and use UVM-ML for running RTL (which requires VCS). However, the UVM-SystemC component in UVM-ML seems to be a 'minimalistic' version of UVM-SystemC, and there are some differences between the two. For example, UVM-ML's UVM-SystemC employs a barrier mechanism for phases, while UVM-SystemC uses an objection mechanism.

  Is it possible to combine UVM-SystemC and UVM-ML in the same testbench environment?