-
Posts
129 -
Joined
-
Last visited
-
Days Won
3
Content Type
Profiles
Forums
Downloads
Events
Topics posted by ljepson74
-
UVM 1.2 , run_phase deprecation, and pre-compiling uvm base class
By ljepson74, in UVM (Pre-IEEE) Methodology and BCL Forum
- 2 replies
- 2,396 views
-
ncvlog: *E,EXPENC - Expecting the keyword 'endclass'.
By ljepson74, in UVM SystemVerilog Discussions
- ncvlog
- uvm_analysis_imp
- (and 3 more)
- 1 reply
- 8,892 views
-
how to (best) delay the start of built-in UVM register test stimulus
By ljepson74, in UVM SystemVerilog Discussions
- register layer
- register
- (and 3 more)
- 1 reply
- 4,899 views
-
SV assertion comparing multicycle data bus - specific question
By ljepson74, in UVM SystemVerilog Discussions
- 3 replies
- 6,156 views
-
std::randomize( vs. randomize( vs. this.randomize( and scope
By ljepson74, in UVM SystemVerilog Discussions
- randomize
- std::randomize
- (and 2 more)
- 3 replies
- 51,262 views
-
uvm_scoreboard requires analysis import to compile. why?
By ljepson74, in UVM SystemVerilog Discussions
- irun
- uvm_scoreboard
- (and 4 more)
- 4 replies
- 4,241 views
-
uvm_cmdline_processor get_arg_value/s to receive hex
By ljepson74, in UVM SystemVerilog Discussions
- uvm_cmdline_processor
- get_arg_value
- (and 6 more)
- 0 replies
- 4,911 views
-
UVM_ACTIVE data type....bit or int ?
By ljepson74, in UVM SystemVerilog Discussions
- uvm_config_db
- UVM_ACTIVE
- (and 6 more)
- 3 replies
- 12,927 views
-
SystemVerilog/UVM Support Group - Silicon Valley
By ljepson74, in UVM Commercial Announcements
- UVM
- SystemVerilog
- (and 6 more)
- 0 replies
- 2,543 views
-
style: X / $isunknown checking:where? bind file,interface,monitor?
By ljepson74, in UVM SystemVerilog Discussions
- 0 replies
- 1,126 views
-
- 2 replies
- 5,020 views