Jump to content

ljepson74

Members
  • Content Count

    128
  • Joined

  • Last visited

  • Days Won

    3

Everything posted by ljepson74

  1. Note/Clarification: With VCS 2019.06 and Riviera Pro 2020.04, the code in the original post works as I expected. cg_fa[0] - Coverage=78.12 % cg_fa[1] - Coverage=1.56 % I try to write code which has "universal" support across "all" simulators. Is the difference across simulators due to ambiguity in the LRM? Is some aspect of my code using a poor style? How can this code be improved for more universal simulator support? (I am trying to avoid publically contrasting simulators, which afaik is verboten.)
  2. Using an array of class objects which have a covergroup in them, I've run into the following problems. I look for a solution which is supported by all/most simulators. This topic array seems to be a common issue, based upon web search results. ERROR TYPE0: Same coverage is recorded for both covergroups, despite option.per_instance=1 being used. # vsim -voptargs=+acc=npr # cg_fa[0] - Coverage=81.25 % # cg_fa[1] - Coverage=81.25 % ERROR TYPE1: Compile error with another simulator cg_fa[0] - Coverage=xmsim: *N,COVNSM: (File: ./testbench.sv, Line: 42):(Time: 0 FS + 0) Sampling of
  3. How can I write the following sequence? If sequence A happens, then sequence A may not happen again until either sequence B or sequence C happens. An example of the sequences might be: sequence seqA; ($rose(A)) ##1 $fell(A); //single cycle A pulse endsequence sequence seqB; B[->1]; //B high for 1 cycle endsequence sequence seqC; (1[*10]); //10 clk cylces endsequence It is important in this question that seqA is a sequence, so that we are not just checking seqA |-> (!A throughout (seqB or seqC)) (For this simple example, afte
  4. Thanks, David. Your response got me reading about the quality of RNGs (which was nice, but not my goal) and your initial example was in C. I was just looking for a way to make a simple system call (from SystemVerilog) to set the seed; to run a handful of times in succession with different seeds. I didn’t read far enough into Doug’s paper**1 to see his example code that you used in your most recent example. % head -4 /dev/urandom | od -N 4 -D -A n | awk '{print $1}' Your second example, www.edaplayground.com/x/Zve, is what I was looking for. Thank you. I use it as you suggeste
  5. basarts, Good point. I had looked into “expr” and some other commands besides date, but should have been looking at exit codes. (I must have been looking at various SV procedures that can be called as either tasks or functions, for too long.) It seems any solution for my original question would require some external, non-SystemVerilog code and a DPI or similar call, which I’ll avoid for my current study purposes on edaplayground. Thanks.
  6. Can a distribution value_range be a list? Or is there way to achieve the same result using "dist"? As shown by non-working example code, I try to do something like this: bit [1:0] twobits; assert(std::randomize(twobits) with {twobits dist {2'b10:=50, inside{2'b00,2'b11,2'b01;}:/50};} ); //INCORRECT assert(std::randomize(twobits) with {twobits dist {2'b10:=50, [2'b00,2'b11,2'b01]:/50};} ); //INCORRECT "18.5.4 Distribution" image snippet from IEEE_Std1800-2017 LRM attached. Is there (isn't there) a way that value_range can be a list of choices, which
  7. Thanks a lot, David. My objective here is simply to be able to push "Run" on edaplayground a few times (usually <5), and to see different results. On Questa, I can use "-svseed=random". I don't know the settings for all of the simulators, so tried an experiment to generate random seeds 100% from within SystemVerilog, as I wrote above (rather than using compiler/simulator switches). For my purposes, if the randomess is not very good ... I don't care. The quality of the randomness is not my objective here. Thanks for that detailed reply, however. You and Doug are great teachers. I'
  8. Does $system() really return an int when called as a function? (Perhaps no one has implemented this part of the LRM?) int myseed; myseed = $system("date"); //should output "return value of the call to system() with data type int" quote source: IEEE_Std1800-2017 Section 20.18.1 $system I have not been able to get a non-0 return value, as far as I can tell. Am I doing something incorretly or is this not implemented? What if $system("date") is called? I suppose the "date" system output is longer than 32b, so perhaps the lowest bits are all 0s and the upper ones that c
  9. @kurtlin , do you know this by chance? I am looking for each VCS simulation 'run' to use a different seed. (I'm using EDAPlayground, so don't have access to a set of user guides.) On a related note to compile switches, besides replacing -sverilog with -sv=2009, as you showed in another thread **1, I found this below. (I suspect that -sv=2009 is a superset of "-assert svaext". So, I'll probably stick with that. Thanks again.) Perhaps I might set the seed from within the code, performing a string operation on the output of $system("date") **1:
  10. Yes, thanks Dave. (I saw that. I was trying not to make comparisons between them, lest I violate some benchmarking rule or such.) (I'll move on to another topic now, as I work to get the rust off of my SystemVerilog skills.)
  11. Thank you. I could not (easily, so I gave up) find information about the compiler switches online. a) -sv=2009 works and the compiler error disappears b) The assertion AS_TRUE5_STRONG does not fail, as expected, based on the LRM description of "strong". IEEE_Std1800-2017 : 16.12.2 Sequence property Aren't the clock cycles of the sequence which do not complete (because the simulation ends) empty matches?
  12. The below assertions check that gnt is not high for consecutive clk cycles. Q1: v1 vs. v2: Are there benefits or relevant differences between these styles. Q2: v2 vs. v3: Does the placement of delay matter? Besides for end of simulation termination. The questions are mainly about whether some style is better for the simulator, or there is some non-obvious situation I should consider. module top; bit clk, gnt; bit [19:0] gnt_a; initial begin gnt_a = 20'b0011001010_0000001101; #200 $finish; end assign gnt = gnt_a[19]; always clk = #5 ~clk; always
  13. Does VCS 2019.06 support strong and weak? (Or is there a VCS switch needed to use LRM 2009+?) I get the following error with the code below. Error-[IND] Identifier not declared testbench.sv, 15 Identifier 'weak' has not been declared yet. If this error is not expected, please check if you have set `default_nettype to none. Error-[IND] Identifier not declared testbench.sv, 16 Identifier 'strong' has not been declared yet. If this error is not expected, please check if you have set `default_nettype to none. Code: //Weak & Strong seem to not work in VCS 20
  14. Synopsys VCS: What is the run option to use a random seed?
  15. mastrick, Thanks for that. That is a very good point. For forums or any sort of Q&A I try to show the focus of the post as succinctly as possible. Doing so, I sometimes use styles I wouldn't ordinarily, like skipping a "begin ... end" when it is not required because there is only one line of code. (I like to always use begin/end and heavily use parentheses to be explicit.) I agree with your point. Why am I responding to threads from 4 years ago, one might ask? Because after 3 years of not using UVM and almost no SystemVerilog, I am trying to get the rust off
  16. Note: There will be a reply coming soon by user “jdickol”. (He recently registered, so his reply likely needs moderator approval, but he messaged me directly.) Thanks for the solution, jdickol. This is how the constraint can be written: constraint total_weight { (animal_da.sum with (item.weight)) == 100; } Output: # animal weight:39 # animal weight:24 # animal weight:37 # ***********************Total weight: 100 # animal weight: 7 # animal weight:36 # animal weight:57 # ***********************Total weight: 100 # animal weight:48 # animal weight:28 # anima
  17. I've simplified the example. Goal: Using constraints in group_of_animals_c, can we constrain the sum of the animal weights? I'd prefer to avoid procedural code in functions being called. My goal is understand if/how a constraint might reach thru class handles and affect properties in the objects contained by the object which is being randomized. //Class animal_c has a property "weight". //For an array of animal_c (as part of class group_of_animals_c), // the total weight of the animals should be 100. //How can this be done with constraints? //Can a constraint expression refe
  18. Thanks, David. Instead of using post_randomize(), I moved some of the work to pre_randomize(). That helped. I show the code below. But to get to the heart of the question I have, I will try to further shrink the code in a subsequent post. //Class animal_c has a property "weight". //A dynamic array is generated where each element points to an animal. //The cumulative weight of the animals should be 100. //How can this be done with constraints? //Can a constraint expression reference properties referenced by handles? // //My goal is to better understand contraints, so I attempt to stuff
  19. Can a single constraint be used across an array of objects? i.e. affecting the relation between a property which exists in each of those objects? I'm trying to do something like an array reduction or sum, but instead of performing it on an array, performing it on the properties of objects in an array. My goal is to better understand the capabilities of constraints. Example below: (I do not show my failed attempts.) //Class animal_c has a property "weight". //A dynamic array is generated where each element points to an animal. //The cumulative weight of the animals should be 1
  20. @uwes, thank you. For better or worse, the project that I work on for this does not use UVM. (Yes, I realize that this is a UVM forum and that my question is just a vanilla SV one.) I'll keep this response you sent in mind for the future and look forward to trying it. That looks like a clear and terse solution - which is what I look for. (Hopefully my next project uses UVM.) @chr_sue, Thanks. But what I try to do is the reverse. i.e. to see if the value of my_string (which is of type string) is one of the my_enum states. So, using the cast style you show, I'd need to cast each s
  21. Is there an easy (concise, maybe one-liner) way to check if a string is 'inside' an enum? i.e. typedef enum {alpha, beta, gamma, delta, epsilon} my_enum; string my_string; my_string = <something>; //I know this is not possible, but I try to do something like this if (my_string inside {my_enum.names}) // where names would imply all of the enumeration option strings I try to avoid walking thru all of the enumerated values, which is what I currently do (and which works fine).
  22. *, How can I randomize with a dist and specify a weight for values not being inside a range? class randclass; rand logic [3:0] randvalue; function void post_randomize(); $display("value: %0d",randvalue); endfunction constraint inside_practice { randvalue dist { [3:4] :/ 50, !(inside {[3:4]}) :/ 50 //<--- I try to have a sort of 'others' category here }; } endclass module top; randclass randclass; initial begin randclass = new(); repeat (10) begin randclass.randomize(); end $finish(); end endmo
  23. I recently encountered SVA code which results in different results on different simulators. I've shrunk it to a simple example here. I believe this code should cause an error, but it does not on all tools. Can someone comment on how the 2017 LRM should be interpreted (and perhaps on the code). (I sense someone will comment on the driving signals in the code.) module top; bit clk; logic sig1; logic disable_assert; always begin #5 clk=0; #5 clk=1; end initial begin disable_assert=1'b1; sig1 =1'b0; $display("Hello Wor
  24. What is the proper forum to request that this be more clear in the next LRM release? Should I send that request to the IEEE now, instead of Accellera? Request: 1) "time step" vs "step time" - Use only one or the other (or state their equivalence, to help people who search the doc for the term). 2) Describe relationship between "time step unit" and "time slot".
  25. Both the 2005 and 2017 LRMs contain this statement: The 2017 LRM also states: So, in searching for the definition of "time step", as used in the 2017 LRM, I should have been searching for just "step". In response to my question above, I offer the following definition of the relationship between "time slot" and "time step". A "time step" is the distance between two adjacent "time slot"s, or is simply used to refer to a successive "time slot". i.e. When you advance a "time step", you simply move to the next time slot.
×
×
  • Create New...