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amitrana

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  1. Hi UVM, I want to know about future of system C as a verification language. if we compare system c with systemverilog which will win ?
  2. Hi UVM, IN uvm we pass the name of test at run time with +UVM_TEST_NAME . Can we do the same with the parameterized seqence,passing their name on command line by using the $value$plusargs. Second can we run a parameterized test in uvm?
  3. Hi naveeng, You can call $assertoff anywhere in your testbench. Best place to call is ,In sequence. For example modue top ; Ass:assert property(p); endmodule In sequence body task you can do like that, task body(); $assertoff(0,$root.top.Ass); endtask
  4. Hi Jishnu, You can raise the objection from sequence,for example in sequence you can do like that in pre_body if(starting_phase !=null) starting_phase.raise_objection(starting_phase) and in post_body drop the objection.
  5. HI , Casting can be done from a child to parent class. Forexample, class A; endclass class B extends A; endclass module top; A a; B b; initial begin b=new(); void'($cast(a,); endmodule But in your case you are doing reverse from parent to child ,that's an error. end
  6. Hi Jishnu, Are you rasing and droping objection from main_phase. Plz use objection in main phase.
  7. Hi Jishnu, for wait process use wait_ptrigger(), to sense the event in the current time value,it removes the race condition ,between triggeriing process and waiting process
  8. Hi bverma, There is no direct method of setting the queue in the resource data base. You can make the wrapper class object and then set that object in resource data base. other solution is by using the loop and setting each element of array or queue.
  9. Hi UVM WORLD, I wanna know which approach is better (1) using config_db in sequence for setting control parameter in UVC OR (2) Concept of virtual Sequencer.
  10. Hi Sean Chou, You can view my another post regarding the uvm_in_order_comparator. In this post i have attached my sample code. Please review it , if you could help me. Thanks in advance.
  11. Hi SeanChou, I tried your suggestion,But it did'n work. But I found the solution in different way. Thanks for your valuable effort.
  12. Hi guys , I downloaded the verilog_systemverilog.vim.tar from UVM_WORD to highlighting the uvm keywords colour ,but it did'n work. Any Idea?
  13. Hi Disha, `uvm_sequence_utils is deprecated from the UVM. please use uvm_object_util.Also see your sequencer code if you used uvm_update_sequence_lib_and_item plz comment it and rerun the code. I hope it will work in your case.
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