UVM
49 files
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A methodology for stacking UVCs
By sdonofrio
This contribution describes a "simple" methodology that allows for creating UVM Verification Components (UVCs) that have the flexibility to optionally be connected to other UVCs. This methodology helps promote easier vertical and horizontal reuse. This topic was presented at Accellera Systems Initiative Day at DVCon in the UVM: Ready, Set, Deploy session.
The contribution includes:
(1) A stacking UVC UVM example that runs with the any of the 3 big EDA vendor simulators
(2) A paper called "StackingUVCs.pdf" that describes the methodology and the accompanied example in detail
To use:
>>tar xvf stack_example.tgz
Then read the "SIMPLE_README.txt" file for information on running the example and read the "StackingUVCs.pdf" for details on the methodology and a description of the example.
For any issues or if you would like to learn more about Paradigm Works UVM methodlogies contact us at: pw-support@paradigm-works.com.
836 downloads
0 comments
Submitted
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Appnote: Migrating from OVM to UVM-1.0
By jlrose
Migrating environments from OVM to UVM is largely a matter of changing Os to Us. However, functional changes to phasing and configuration, along with the deprecation string based sequence library necessitate some changes to an OVM environment to make it run with UVM-1.0. This document describes how to migrate to UVM-1.0, but this document does not go into any deep discussion on new UVM-1.0 features.
3,550 downloads
0 comments
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Building UVM Register class environment for Serial Protocols
By MehulKumar
UVM user guide explains in detail how a model is integrated for a parallel interface. This paper discusses the use of UVM register classes when verifying register accesses through a serial port (e.g., JTAG) on the DUT.
3,330 downloads
0 comments
Submitted
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Cadence Reset Example and Package
By uwes
A small package illustrating a method to perform
UVC resets in UVM without phasing interaction.
The package includes 4 examples and documentation showing the package in action
/uwe
728 downloads
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Cadence UVM_RGM2.6.1 release
By vishal.jain
UVM_RGM2.6.1 is the UVM version of the Cadence Register and Memory package that has been tested by multiple users on all major commercial simulators.
Bug Fixed:
Fixed issue with syncing to VHDL. Register overlap check error with end address Backdoor read of register fields was not properly masked Filtering of registers having unknown value is now only for rd_all regs seq Enhancements:
Allowed backdoor write to read-only fields Allowed register's reset value over-ride using plusArgs Added register array delete at the end of built-in-seq Added support field-level backdoor access for shared register Modified shared_reg_backdoor example and added ipxact file Removed all uvm deprication warnings from examples Added support for VHDL backdoor std_ulogic_[ports |signals | vectorSignals] Modified all headers of XML files to get schema from http Added objection to built-in-sequences Added a global field to mask-out comparison of all non-read-write fields Added a global field to enable warning when accessed address is outside container1,197 downloads
0 comments
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Cadence UVM_RGM2.7.5 release
By vishal.jain
UVM_RGM2.7.5 is the UVM version of the Cadence Register and Memory package that has been tested by multiple users on all major commercial simulators.
Bug Fixed:
Fixed issue with backdoor read for special read fields Fixed issue with sync for special read fields Guarded exclude names with empty string match Fixed filtering by breaking immediately when condition matches
Walking one built-in-seq did not create the regOp when writing. Mode based register enum field macro having wrong case statement Typo in DPI file (vhpiHandleT changed to vpiHandle) Check for address overlap for indirect / shared and mode-based corrected
Modified the burst rd-wr testcase to have response Include / exclude addresses, get_config_object issue with reference handle pass
Enhancements: Added support for mode based registers having separate storage Added stand-alone examples for mode-based registers Fixed the typo in sequence macro file when it error Shared register treated as RW register when filtering using condition Shared-indirect register not handled correctly by built-in-sequences Missing clone bit in get_config_object of address_range in sequence library1,743 downloads
Submitted
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Code examples for parameterized interfaces
By pratta
Code examples that demonstrate the problems that parameterized interfaces present for reuseable VIP design and ways to overcome these limitations.
663 downloads
0 comments
Submitted
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ES level UVM concept
By David Black
The diagram here relates to UVM methodology discussion <http://forums.accellera.org/topic/2137-uvm-for-esl-dut-verification/#entry8274> on connecting UVM to an ES level model (i.e. SystemC)...
77 downloads
0 comments
Submitted
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Fine Grain Control of Verbosity of ID in a component
This provided fine grain control of controlling verbosity of different IDs in same component.
The default mechanism somehow does not work for more than one ID.
117 downloads
0 comments
Submitted
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Fixed report server
By Gunther
When changing verbosity in the report_catcher (including setting verbosity when changing severity to UVM_INFO), the reporting does not work as expected. This fixes it.
240 downloads
0 comments
Submitted
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Flexible UVM Components: Configuring Bus Functional Models
By Gunther
This is the example code from the article "Flexible UVM Components: Configuring Bus Functional Models" in the Verification Horizon, June 2013.
234 downloads
0 comments
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flexible-indirect-registers-with-uvm.zip
By uwes
hi,
this archive contains the code for a framework to build indirect registers in a flexible fashion. More insight are shown at dvcon2017-us
/uwe
106 downloads
0 comments
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Interface registry
By uwes
hi,
this is the source code for the interface registry along with 3 examples and the paper/ppt from dvcon2015 illustrating the package. The package itself provides a simple scheme to connect DUV and TB using bind, interface self registration and a database.
regards
/uwe
212 downloads
0 comments
Submitted
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0 comments
Submitted
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Linear PCM integrated example test bench 0.5
By petermonsson
A simple integrated example test bench for people who want to learn UVM.
This is pre-alpha, unreviewed and buggy code. If you use this as a basis for anything other than reviewing it for bugs then you're on your own.
If you tape-out something based on this you will waste time and money.
See the README for more information
764 downloads
0 comments
Submitted
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Mastering UVM: UVM Heartbeat
By DavidLarson
The uvm_heartbeat is a sorely underused jem that cuts out wasted simulation time. What is it, how do you use it and why should you care? I will show you.
521 downloads
0 comments
Submitted
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Multi-language example: SC reference model in UVM SV testbench
By phuynh
This example shows how to integrate a SystemC reference model into a UVM SystemVerilog testbench. The connections between SC-SV are done using TLM-1.0 and the multi-language library from Cadence.
686 downloads
0 comments
Submitted
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OVM2.1.1 to UVM1.0EA Migration Script
In 90%+ of the cases the simple search/replace ovm* with uvm* will work to get you from OVM to UVM.
Heavy OVM users (callbacks) or legacy ones (avm*, urm*) could use a more precise migration which will indicate deprecated types, deprecated macros, method signature changes etc.
The attached refactoring script contains all the differences between OVM2.1.1 and UVM1.0EA. The last few lines are text "ovm*" to "uvm*", the rest are:
removed macros removed classes removed fields removed methods renamed macros renamed classes renamed methods method signature changes (more/less arguments) macro signature changes (more/less arguments) DVT helps the OVM2UVM migration, including the capability to apply this or any other refactoring script. For more details: www.dvteclipse.com/documentation/sv/OVM_to_UVM_Migration.html and www.dvteclipse.com/documentation/sv/Refactoring_Scripts.html536 downloads
0 comments
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PW UVM Scoreboard Version 1.0
By Ambar Sarkar
The scoreboard package is a ready-to-use utility for verifying
data integrity in an UVM Testbench.
The package is UVM compliant. It is suitable for UVM-compliant UVCs and environments.
This version of scoreboard supports the following:
o Scoreboarding through TLM interfaces
o Scoreboarding through procedural interfaces
o On the fly multiple stream support
o Both in-order and out-of-order checking
o Creation of complex DUT-specific transfer functions
o Timeout checking
o Hooks for error handling
o Extendable
1,672 downloads
Submitted
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Run-Time Phasing in the UVM: The Long Lost User's Guide
Since the release of the UVM 1.0, one of the least documented features of the methodology has been the Run-Time Phasing solution. Due to this lack of documentation, many users were immediately turned off from trying to use this new area of the methodology. Even more unfortunate were those users who were brave enough to try and blaze the trail, but were quickly mired down in misuse, misinterpretation, and a general lack of support. This lack of documentation, combined with a general misunderstanding of what Run-time phasing was intended to solve, lead to many users labeling it as “unsafe”, and “overly complicated.”
This document strives to remove the veil of confusion which the UVM’s Run-time phasing is wrapped in, by clarifying its intent and showing how easy it is to build very powerful stimulus.
521 downloads
Submitted
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Simple perl based UCV buider
By cdnmcgrath
I have uploaded a copy of my OVM template genarator updated for UVM. Basically, I changed all OVM/ovm strings to UVM/uvm. You will need to set the environment variable UVMHOME to use the generated "jrun" script. You can email me with any Q's - my email is in the perl script. The simplest way to run:
perl juvb.pl
cd base/examples
setenv UVMHOME <path to UVM install>
jrun
or
perl juvb.pl template=cdn_yapp_uvc.tpl (or you own custom template).
It supports only basic int datatypes in the sequence item class.
It's only intended to get you started and "over the hump". It's
not intended to replace the official template generators.
Happy UVMing....
743 downloads
0 comments
Submitted
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Simple UVM 1.1 UVC template generator - v1.10
By cdnmcgrath
Updated with a few bug fixes. Two minor new features added with v1.10:
-use_seqr : by default, no sequencer component is created, this switch willforce a custom uvm_sequencer component to be generated (not available with -one_file)
-one_file : generate simple uvc in single file - for building small examples1,259 downloads
0 comments
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SMTDV make your test env more smart
By funningboy
https://github.com/funningboy/smtdv
SMTDV -Ver 1.1
2016
SMTDV is a lightweight verification framework based on UVM 1.1d,
user can use/override it more easily to set up their verification environment at moudle level(functional check) and
system level(cosim), that also supports 3rd part lib as sqlte3 db to export/import valid transactions.
----------------------------------------
SMTDV flow overview
----------------------------------------
kernel: base lib import, UVM_ML, systemc
lib: uvc, common lib as middleware lib
script: call, run, unittest
dpi: 3rd part lib, sqlite3, stl, util lib
designs: DUT
test: test env
-----------------------------------------
Getting Started
-----------------------------------------
1. setup $SMTDV_HOME as default root
%setenv $SMTDV_HOME <smtdv_install_area>
%set $PATH = ${SMTDV_HOME}/script
2. prepare .core file
.core file uses section/token key to define preloading files and simulation args,
that can be read more clear and easily as Makefile
reserved sections
[main] : define os.getenv, and opts
[cores]: import dependey .cores
[systemverilog]: define systemverilog include_files, include_dirs, and lib
[verilog]: define verilog include_files, include_dirs, and lib
[systemc]: define systemc include_files, include_dirs, and lib
[sharedlib]: the sharedlib import as .so or *.a
[ius]: use IUS as default simulator
[mti]: use MTI as default simulator
ex:
lib/smtdv_common/smtdv_common.core
lib/smtdv_apb_uvc/sim/smtdv_apb.core
3. prepare required tool and lib
% python >= 2.7.3
% gcc, flex, yacc, sqlite3,
% IUS >= 13.10, MTI >= 10.4
4. build up 3rd part lib
4.1 sqlite3 dpi interface build/test
%cd dpi/sqlite3
%./run.sh
%./a.out
4.1.2 run as systemverilog interface unittest
% cd dpi/sqlite3/test
%python ../../../script/run.py --file test_smtdv_sqlite3.core
4.2 stl interface build/test
4.2.1 stl dpi interface build/test,
stl, it's a raw database to record bus(AXI/AHB/APB) transaction and layer info decoded as package
and frame
%cd dpi/stl
%./run.sh
%./a.out
4.2.2 run as systemverilog interface unittest
% cd dpi/stl/test
%python ../../../script/run.py --file test_smtdv_stl.core
5 UVC one on one (Master/Slave) basic test
ref:
./lib/smtdv_apb_uvc/README
6 module level test (cdnbus) test
ref:
./lib
50 downloads
0 comments
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The Easier UVM Coding Guidelines
By aynsley
This document is a printable version of the Easier UVM Coding Guidelines from Doulos. You are free to use these guidelines directly, to merge them into your own company-specific UVM coding guidelines, or merely to borrow some of the ideas.
These coding guidelines are offered by Doulos for the benefit of the UVM community. They are not officially endorsed by Accellera.
496 downloads
0 comments
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updated juvb template generator for UVM-1.1
By cdnmcgrath
First cut of UVM 1.1 template generator. I have incorporated all the key changes from OVM 2.1.1 and UVM 1.0ea to UVM 1.1. To use "perl juvb11.pl -help". Assumes perl is in your path. I plan to make some additional changes including adding the new sequence library setup, driving a couple of dummy ports to see real waveforms, and adding a basic scoreboad, Note this is a VERY BASIC template genarator intended to get a user started with UVM - not intended to replace offically supported vendor template generators. This is AE-ware. Note that it still generates "jrun" and "jclean" scripts and should run out-of-the box. User will need to set UVMHOME env. var to point to UVM-1.1 installation. Good luck!
406 downloads
0 comments
Submitted