Multi-language example: SC reference model in UVM SV testbench

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https://forums.accellera.org/files/file/85-multi-language-example-sc-reference-model-in-uvm-sv-testbench/

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This example shows how to integrate a SystemC reference model into a UVM SystemVerilog testbench. The connections between SC-SV are done using TLM-1.0 and the multi-language library from Cadence.

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