Jump to content

Multi-language example: SC reference model in UVM SV testbench

About This File

 This example shows how to integrate a SystemC reference model into a UVM SystemVerilog testbench. The connections between SC-SV are done using TLM-1.0 and the multi-language library from Cadence.

User Feedback

Recommended Comments

There are no comments to display.

Join the conversation

You can post now and register later. If you have an account, sign in now to post with your account.
Note: Your post will require moderator approval before it will be visible.

Add a comment...

×   Pasted as rich text.   Paste as plain text instead

  Only 75 emoji are allowed.

×   Your link has been automatically embedded.   Display as a link instead

×   Your previous content has been restored.   Clear editor

×   You cannot paste images directly. Upload or insert images from URL.

  • Create New...