818 downloadsThis contribution describes a "simple" methodology that allows for creating UVM Verification Components (UVCs) that have the flexibility to optionally be connected to other UVCs. This methodology helps promote easier vertical and horizontal reuse. This topic was presented at Accellera Systems Initiative Day at DVCon in the UVM: Ready, Set, Deploy session. The contribution includes: (1) A stacking UVC UVM example that runs with the any of the 3 big EDA vendor simulators (2) A paper called "StackingUVCs.pdf" that describes the methodology and the accompanied example in detail To use: >>
Paradigm Work's offers a free scoreboard frame work located at: http://www.design-reuse.com/news/exit/?id=27392&url=http://www.uvmworld.org/contributions-details.php?id=100&keywords=PW_UVM_Scoreboard_Version_1.0 In addition, it sounds like you need to shadow memory on top of the scoreboard. Usually, I use SV associative arrays to implement a simple shadow model. Additionally, with UVM 1.x there appears to be a uvm memory model with peek and poke capabilities. See section 5 in the UVM User Guide for details. Hope this helps.