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    This contribution describes a "simple" methodology that allows for creating UVM Verification Components (UVCs) that have the flexibility to optionally be connected to other UVCs. This methodology helps promote easier vertical and horizontal reuse. This topic was presented at Accellera Systems Initiative Day at DVCon in the UVM: Ready, Set, Deploy session. The contribution includes: (1) A stacking UVC UVM example that runs with the any of the 3 big EDA vendor simulators (2) A paper called "StackingUVCs.pdf" that describes the methodology and the accompanied example in detail To use: >>
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