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DavidLarson's Achievements

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  1. For 1: You can use the schema files provided by Accellera. Run them with xmllint. For 2: No. Pretty sure there isn't an open-source tool to do that for you.
  2. Forget my last question. I believe I figured it out. Now to figure out how to put hdl_paths in a hierarchy....
  3. Thank you Erwin. Yes that does help. Our situation is a little different, where we have a hierarchy of components, each with their own bank of registers. So, we won't be looking to connect sibling components, but connections would be from parents to children. Can that be done with IPXACT?
  4. Hi Erwin, Thank you for the info. I've been reading through the User Guide and it doesn't seem to provide all the info I need to do this. For example, in section 3.1.6 it says: Yet, it doesn't explain how to put a memoryMap in an addressSpace. You can only put segments in addressSpaces, not memoryMaps. Can you please provide an example of what that would look like? Regards, David
  5. I'm going through the HAL documentation and it looks l like the only languages that HAL supports are: Verilog, VHDL, SystemC and e. No system verilog. Rats.
  6. I have found a related problem. When you need to send a 1 to a W1C register field, the normal flow doesn't work: register_model.register.w1c_field.set(1); // <--- this is set to 0 internally register_model.register.update(status); This is clearly not what the user expects. What is the correct flow for these registers?
  7. I just compiled your code (I added the endclass keyword): class addr_hole_seq extends uvm_sequence # (uvm_sequence_item); `uvm_object_utils(addr_hole_seq) endclass and it compiled fine. Now you need to check elsewhere ... the code preceding this, how you are compiling, etc.
  8. I see errors like this when the macro is not called correctly. Check these: If the object is parameterized you should be using `uvm_object_param_utils (<object_name>#(<parameters>)). make sure that the argument to the macro contains the name of the class and there are no typos. Make sure the registration macro isn't called more than once. Other than that, it would be helpful to see your source code.
  9. Hi Jadec, I agree that the get function is expensive, but calling it from the sequencer (rather than the sequence) is just as expensive since it is called the same number of times either way. David
  10. Hi mrforever, I just checked the UVM 1.1d library and the macro still exists. (phew!) You should email your question to support@synopsys.com (I think that's the right address) and a FAE will get back to you. Good luck! David
  11. If you are using a pre-compiled version of the UVM library then the macro will not change it. If you are not using a pre-compiled UVM library, then I would contact the Synopsys FAE and ask them what needs to change in your compile flow. I'm sure that the fix is something simple.
  12. Yes, I agree Logger. Since you have several items in your TB needing this setting then using the configuration DB is the way to go (vs. setting the items directly). BTW: Have you tried using uvm_resource_db instead?
  13. Hi mrforever, It looks like you are passing in the UVM_USE_CALLBACKS_OBJECTION_FOR_TEST_DONE macro as a run-time argument. It needs to be passed in during the compilation phase with a +define. Good luck and enjoy the heartbeat! David
  14. The uvm_config_db is used primarily to configure uvm_components. This is a snippet from the reference manual (italics are mine): The uvm_config_db class provides a convenience interface on top of the uvm_resource_db to simplify the basic interface that is used for configuring uvm_component instances. Regardless, I find that it is far better to set the variable directly. The real power of the resource DB is when the wildcard can be used in the path, but that doesn't apply to you in this case.
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