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DavidLarson

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  1. For 1: You can use the schema files provided by Accellera. Run them with xmllint. For 2: No. Pretty sure there isn't an open-source tool to do that for you.
  2. Forget my last question. I believe I figured it out. Now to figure out how to put hdl_paths in a hierarchy....
  3. Thank you Erwin. Yes that does help. Our situation is a little different, where we have a hierarchy of components, each with their own bank of registers. So, we won't be looking to connect sibling components, but connections would be from parents to children. Can that be done with IPXACT?
  4. Hi Erwin, Thank you for the info. I've been reading through the User Guide and it doesn't seem to provide all the info I need to do this. For example, in section 3.1.6 it says: Yet, it doesn't explain how to put a memoryMap in an addressSpace. You can only put segments in addressSpaces, not memoryMaps. Can you please provide an example of what that would look like? Regards, David
  5. I'm going through the HAL documentation and it looks l like the only languages that HAL supports are: Verilog, VHDL, SystemC and e. No system verilog. Rats.
  6. I can see some very old code that should be cleaned up (such as the uvm_in_order_comparator). What is the timeline for a general code clean up?
  7. 477 downloads

    The uvm_heartbeat is a sorely underused jem that cuts out wasted simulation time. What is it, how do you use it and why should you care? I will show you.
  8. 635 downloads

    This update adds a section that addresses how to connect harnesses to arrays of sub-modules in a virtual harness. Harnesses are a proven methodology to hierarchically reuse interface connections from the block to the chip level.Included in the package are instructions for both UVM and OVM test benches.
  9. 228 downloads

    Update: Added example code and clarifications in the documentation. Harnesses are a proven methodology to hierarchically reuse interface connections from the block to the chip level. Included in the package are instructions for both UVM and OVM test benches.
  10. 480 downloads

    Harnesses are a proven methodology to hierarchically reuse interface connections from the block to the chip level. Included in the package are instructions for both UVM and OVM test benches.
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