Cadence UVM_RGM2.6.1 release

UVM_RGM2.6.1 is the UVM version of the Cadence Register and Memory package that has been tested by multiple users on all major commercial simulators.

Bug Fixed:

• Fixed issue with syncing to VHDL.
• Register overlap check error with end address
• Backdoor read of register fields was not properly masked
• Filtering of registers having unknown value is now only for rd_all regs seq

• Allowed backdoor write to read-only fields
• Allowed register's reset value over-ride using plusArgs
• Added register array delete at the end of built-in-seq
• Added support field-level backdoor access for shared register
• Modified shared_reg_backdoor example and added ipxact file
• Removed all uvm deprication warnings from examples
• Added support for VHDL backdoor std_ulogic_[ports |signals | vectorSignals]
• Modified all headers of XML files to get schema from http
• Added objection to built-in-sequences
• Added a global field to mask-out comparison of all non-read-write fields
• Added a global field to enable warning when accessed address is outside container