uwes
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uwes last won the day on August 15 2020
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advaneharshal started following uwes
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ljepson74 reacted to a post in a topic: uvm_builtin_reg_test_seq & default sequences
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ljepson74 reacted to a post in a topic: Check if string is 'inside' an enum
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Check if string is 'inside' an enum
uwes replied to ljepson74's topic in UVM SystemVerilog Discussions
have a look at uvm_enum_wrapper in uvm12+. you could simply do the following (untested) class myenumwrapper#(type T) extends uvm_enum_wrapper#(T); static function bit is_inside(string x); return map.exists(x); endfunction endclass // and later myenumwrapper#(my_enum)::is_inside("alpha") /uwe -
Vijay Kumar Panasa reacted to a file: Interface registry
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sounds as if the file ahb_bridge.sv is corrupt.
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uvm_reg_field.get_access() method returns wrong value
uwes replied to Petr Kobiersky's topic in UVM SystemVerilog Discussions
hi, could it be that this is a UVM earlier than UVM-IEEE? if thats the case then you probably hit a known issue. /uwe -
hi, you are using uvm1.2 with the uvm11 version of the cadence extensions. please choose one of the following 1. use the cadence distributed version in your install 'irun -uvmhome CDNS-1.2 ....' (no need for any other uvm compile/flags ...) 2. you point to the right extensions 'irun -uvmhome ...yourpath... -uvmexthome <cdnsinstall>/tools/methodology/UVM/CDNS-1.2 ....' i also see that you are using a very old version of ius and it is suggested to use a more recent one. /uwe
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hi, there are two questions you ask: 1. why is auto_predict=off the default?: normally auto_predict==off is the more versatile mode of operation. it works through a monitor when the real transaction is seen on the bus, it works in passive mode, it works with back-to-back transfers etc. 2. does setting auto-predict after the write help?: simply no. for auto predict to work the driver-sequencer handshake has to wait till the real end of transaction on the bus and it has to be switched on before the read/write operation.
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u24c02 reacted to a post in a topic: Unrecognized system task or function: $cdn_ahb_access
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Unrecognized system task or function: $cdn_ahb_access
uwes replied to u24c02's topic in UVM Simulator Specific Issues
hi, the technical part of the error is that you missed to include the system functions into your command invication (something like -loadvpi, -svlib or similar). nevertheless i would recommend the file a support ticket to have this resolved. /uwe -
report_phase UVM report_phase not being executed
uwes replied to Joe Twwedie's topic in UVM SystemVerilog Discussions
hello, again - its hard to suggest something if you cannot clarify what you mean with 'kill'. this could a everything from - killing via 'kill -9' on the os level (or via signals to the simulator) - $stop,$finish and friends - via calls to uvm api methods - through phase operations/jumps - through a message causing the simulation to end - through a 'coded' natural end - through an end of event (by "killing" the clock) - through an end caused by external code .... /uwe -
report_phase UVM report_phase not being executed
uwes replied to Joe Twwedie's topic in UVM SystemVerilog Discussions
hi to answer the question we need to know 'how' your test is 'killed'. what mechanism is used to terminate? /uwe -
a rand var which divides by 7 and 17 can be divided by 7*17 (since both are prime). so the constraint should be as simple as x % (7*17) == 0 //uwe
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jcvobu reacted to a post in a topic: How to get the value of a string when using the string in a hierarchical path
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unless you wrap the string/int/bit in a class instance this will not work.
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Maybe an error on UVM 1.1d for uvm_reg_map.svh class
uwes replied to joniale's topic in UVM SystemVerilog Discussions
i think this is yet another issue in the register model related to https://accellera.mantishub.io/view.php?id=5446 -
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SystemVerilog/UVM linting - what tools exist ?
uwes replied to ljepson74's topic in UVM Simulator Specific Issues
sv should be supported too in hal. typically hal is more focused on rtl code. /uwe