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IP-XACT Discussion

IP-XACT general discussion.

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94 topics in this forum

  1. Element "arrays/array" of class configurable array in component IPXACT

    By Bhargav,   
    • 3 replies
    • 555 views

  2. Design IPXACT-adHocConnections-InternalPortReferences-left and right attributes

    By Bhargav,   
    • 6 replies
    • 670 views

  3. Component ipxact multiple ports connection

    By harshita,
    • 1 reply
    • 355 views

  4. Missing Register Field specifications

    By UshaKumi,
    • 1 reply
    • 489 views

  5. Validating IPXact

    By NagaSunil,   
    • 2 replies
    • 964 views

  6. Referencing the memoryMap of a sub-component

    By ddc1234,
    • 5 replies
    • 1.2k views

  7. IPXACT for Registers alone for UVM RAL

    By saravanan,   
    • 1 reply
    • 1.3k views

  8. Parameters and parameterized port widths in IPXACT 1685-2009

    By am91,   
    • 3 replies
    • 1.5k views

  9. Up-conversion from 1.0 to 1685-2014

    By hbhatia,   
    • 1 reply
    • 1.4k views

  10. Best practice to specify global memory map for top level design config

    By tjroamer,
    • 2 replies
    • 1.4k views

  11. inclusion of busDefinition in Component

    By Ritu Rathore,   
    • 1 reply
    • 636 views

  12. buildCommand for c/c++ object file

    By Justin Huang,   
    • 5 replies
    • 1.1k views

  13. Interpretation of empty optional element

    By avot,
    • 0 replies
    • 620 views

  14. Purpose of modifiedWriteValue = oneToSet?

    By Michael Tsurikov,
    • 2 replies
    • 1.1k views

  15. IP-XACT : "testable" and "testConstraint"

    By jamal elhaitout,
    • 6 replies
    • 1.2k views

  16. Is to good to add a view to list user guide in component description?

    By Justin Huang,   
    • 1 reply
    • 619 views

  17. xsd to jar

    By ravin,
    • 0 replies
    • 758 views

  18. Duplicated schema tags

    By olofk,
    • 2 replies
    • 733 views

  19. IEEE 1685-2014 and TGI.WSDL specification

    By amal.khailtash,
    • 7 replies
    • 1.5k views

  20. SystemVerilog Interface packaging

    By avot,
    • 4 replies
    • 2.3k views

  21. Is it valid to describe a design whose lower level are not all ip-xact components using ipxact:design?

    By Justin Huang,   
    • 3 replies
    • 745 views

  22. Is there any reference design for TGI library available?

    By Justin Huang,   
    • 1 reply
    • 655 views

  23. clockInterfaceRef and resetInterfaceRef missing in schema

    By tjroamer,
    • 1 reply
    • 674 views

  24. Multiple instances of same uvm_reg_block

    By xxzhao,   
    • 1 reply
    • 1.1k views

  25. Leon2 for 1685-2009

    By Eirik Prestegårdshus,   
    • 1 reply
    • 754 views
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