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Minimal bus description


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If I today have a collection of component/memorymaps IP-XACT files that describe register layouts of various blocks, how could I as simply as possible create a description of a (or perhaps a few) buses and the offsets where those components would be instantiated (perhaps multiple times for each type). The purpose would be simply to describe the global address map as seen from a cpu. To start I'd only need this kind of information:
bus A
   block a : h'1000
   block a : h'2000
   block b : h'3000
   block c : h'5000
bus B
   block b : h'1000
   block b : h'3000
   block b : h'5000
 

This description could later be expanded towards a more complete description of the system. My experience so far is limited to memory maps and their contents.

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Thanks, so to describe the bus I should create a separate component with these bridges.
To then describe the connections of the devices to the bus, should I use a "design" or a hierarchical component (that would use the "component/model" element I think?)?

 

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Yes you need a design to describe component instances and interconnections. Optionally, you can describe a component that references that design (so it becomes an hierarchical component). I consider it good practice to add that hierarchical component always.

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