multidimensional ports mapping to bus interfaces

[Khushi]

Hello

If the abstraction defn specify a port DATA with width 16 and there is a physical port in rtl defined as

output logic [1:0][7:0] data

How do I specify the portMap spection for this ? DO I need to specify the indices. Is the following is a correct representation ?

<ipxact:logicalPort>
               <ipxact:name>DATA</ipxact:name>
              </ipxact:logicalPort>
              <ipxact:physicalPort>
                <ipxact:name>data</ipxact:name>
                <ipxact:partSelect>
                  <ipxact:indices>
                    <ipxact:index>0</ipxact:index>

                   <ipxact:index>1</ipxact:index>
                  </ipxact:indices>
                  <ipxact:range>
                    <ipxact:left>7</ipxact:left>
                    <ipxact:right>0</ipxact:right>
                  </ipxact:range>
                </ipxact:partSelect>
              </ipxact:physicalPort>

Thanks

Khushi

[kock]

Hi Kushi,

Your representation is not correct. Since you want to map all physical port bits you do not need to describe a partSelect element at all. Without partSelect it is assumed that all physical bits are mapped. If you do want to add a partSelect, then no indices are required and your range left is 15 and range right is 0. So you linearize the physical bits. You only need to use indices if you want to map a slice in one dimension of a multidimensional array.

Best regards,
Erwin

[Khushi]

Thank you Erwin.

Just trying to understand when to use indices. Now lets abstraction defn specify two port DATA1 and DATA2 with width 16 each and there is a physical port in rtl defined as

output logic [3:0][7:0] data

We want to map DATA1 -> [1:0][7:0]data and DATA2 -> [3:2][7:0]data, in this case is the following is correct ?

<ipxact:logicalPort>
               <ipxact:name>DATA1</ipxact:name>
              </ipxact:logicalPort>
              <ipxact:physicalPort>
                <ipxact:name>data</ipxact:name>
                <ipxact:partSelect>
                  <ipxact:indices>
                    <ipxact:index>0</ipxact:index>

                   <ipxact:index>1</ipxact:index>
                  </ipxact:indices>
                  <ipxact:range>
                    <ipxact:left>7</ipxact:left>
                    <ipxact:right>0</ipxact:right>
                  </ipxact:range>
                </ipxact:partSelect>
              </ipxact:physicalPort>

<ipxact:logicalPort>

<ipxact:logicalPort>
               <ipxact:name>DATA2</ipxact:name>
              </ipxact:logicalPort>
              <ipxact:physicalPort>
                <ipxact:name>data</ipxact:name>
                <ipxact:partSelect>
                  <ipxact:indices>
                    <ipxact:index>2</ipxact:index>

                   <ipxact:index>3</ipxact:index>
                  </ipxact:indices>
                  <ipxact:range>
                    <ipxact:left>7</ipxact:left>
                    <ipxact:right>0</ipxact:right>
                  </ipxact:range>
                </ipxact:partSelect>
              </ipxact:physicalPort>

<ipxact:logicalPort>

 

Thank you.

[kock]

Hello Kushi,

No that is not correct. When multiple indices are present, they correspond to the dimensions of the defined port, account for array
ranges first, and then account for vector ranges. In your example, there are two indices 0 and 1 for mapping DATA1. You have no array dimensions in the rtl port so 0 and 1 apply to the vector dimensions [3:0][7:0] and you are selecting port element [0][1]. Same for DATA2 where you select port element [2][3]. If you want to express your desired mapping you can use 4 port map elements:

1) data with index 0 and range 7:0 maps to DATA1[7:0]
2) data with index 1 and range 7:0 maps to DATA1[15:8]
3) data with index 2 and range 7:0 maps to DATA2[7:0]
4) data with index 3 and range 7:0 maps to DATA2[15:8]

Best regards,
Erwin

[Khushi]

Thank you Erwin. This clears a lot.

One last related question for following scenario

- The absdef has two ports DATA1 and DATA2 with width 12 each

- RTL has a port output logic [1:0][2:0][3:0] data

In this case if I need to map [0][2:0][3:0] data to DATA1 and [1][2:0][3:0] data to DATA2 then how to specify [2:0][3:0] in physical port as there is only one range element there

So either I can do (with flattening of [2:0][3:0])

1) data with index 0 and range 11:0 maps to DATA1[11:0]
2) data with index 1 and range 11:0 maps to DATA1[11:0]

or 

1) data with index 0,0 and range 3:0 maps to DATA1[3:0]
2) data with index 0,1 and range 3:0 maps to DATA1[7:4]
3) data with index 0,2 and range 3:0 maps to DATA1[11:8]
4) data with index 1,0 and range 3:0 maps to DATA2[3:0]
5) data with index 1,1 and range 3:0 maps to DATA2[7:4]
6) data with index 1,2 and range 3:0 maps to DATA2[11:8]
 

Which one is correct ?

Thanks

[Jason H]

These are SystemVerilog rules, not IP-XACT. As Erwin mentioned, the signal is pure-vector. That means you have to match the "shape". However, abstractionDefinition ports have a more generic width that is not language specific.

You cannot specify

data[0][11:0]

That is invalid. However, you can specify

data[0][2:0]

which is 12 bits, and

data[1][2:0]

which is also 12 bits.

 

In fact, you can just specify data[0] and data[1]. I recommend looking up unpacked arrays in the SystemVerilog LRM.