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Khushi

Interface mode mirroredMaster mirroredSlave

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Hi

Can anyone explain me when to use mirroredMaster  and mirroredSlave interface mode in IP-Xact businterfaces.

I am not able to understand when to use master vs mirroredSlave (or slave vs mirroredmaster). I have a set of bus protocols for which I created a set of busdef/absdef but in component I am not able to decide whether to use master vs missoredSlave and slave vs mirroredMaster.

Can someone explain here in layman terms the different between master and mirroredSlave (slave vs mirroredmaster) and when to use mirror interfaces and what is the consequence in generated netlist.

Thanks

Khushi

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Hi Kushi,

In an abstraction definition, you can describe the properties of logical ports for master, slave, and system interface. For wire ports, the properties are presence, width, and direction. In a bus interface, the component ports mapped onto the logical ports have to obey the semantic consistency rules concerning the directions (SCR 6.* in IEEE 1685-2014). For instance, SCR 6.5, a logical port with direction in can only be mapped onto a component port with direction in, inout, or phantom. For a mirrored bus interface, the direction of the logical port must be reversed.

If an abstraction definition contains logical ports such that for each logical port the direction in a master is mirrored compared to the direction in a slave, and also presence and width are identical in a master and a slave, then from the netlisting point of view there is no difference between a master interface and a mirrored slave interface and also no difference between a slave interface and mirrored master interface. Such an abstraction definition is sometimes called symmetric.

However, if an abstraction definition is asymmetric, then SCRs 6.* imposes different constraints for master/mirrored slave interfaces and slave/mirrored master interfaces. A typical example is a logical clock port (see all AMBA bus definitions). The logical ports PCLK, HCLK, and ACLK have direction in for master and slave interfaces. Another example is IEEE 1149.1 JTAG (see https://www.accellera.org/images/busdefs/busdef_SpiritCons_Accellera_1685-2009_final.zip) where logical ports TDI and TDO have a width of 1 in slave interfaces and no width in master interfaces. As a result you can mapped multiple TDI/TDO bits in a mirrored master interface but only 1 bit in a slave interface.

The use of mirrored and non-mirrored interfaces is not only relevant for connectivity but also for internal addressing in a component. If you use mirrored interfaces then the internal addressing can only be expressed using channels  (from mirrored master to mirrored slave). If you use non-mirrored interfaces then the internal addressing can only be expressed using bridges (from slave to master). It is not possible to describe internal addressing with a combination of mirrored and non-mirrored interfaces (e.g. addressing from a mirroredMaster to a master). As a result, it is not possible to cascade components that use channels for addressing. Hence, my advice is always to use bridges for addressing in combination with non-mirrored interfaces. In my opinion, the use of mirrored interfaces only makes sense in combination with non-addressable bus definitions that are asymmetric. Typically, these are serial protocols such as JTAG, but also I2C, I2S, SPI, and so on. Often they have an output enable logical port with direction out for master and slave interfaces. In that case, you functional IO muxing component needs mirrored master and slave interface to allow the output enable signal to be input. Please see the above referenced accellera.org bus definitions. 

Best regards,
Erwin

 

 

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Thanks Erwin for the detail explanation.

In almost all protocols we have clk and rst signals which are "in" on both master and slave. So does it mean for all such protocols the corresponding bus interface in component should be always mirroredSlave(instead of master) and mirroredMaster(instead of slave)  Or we should not map clk and reset in component bus interface and keep them as master or slave (instead of mirroredSlave or mirroredMaster)

Thanks

Khushi

 

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Hi Kushi,

Clock and reset have direction in because that is the direction from the protocol point of view. Clock and reset signals are generated by clock and reset generators. If you map clock and reset in your master and slave bus interfaces, you need to drive the clock and reset signals. You can do this by inserting a so-called phantom component on the interconnection. A phantom component is a component that only has phantom ports (ports with direction phantom). Here is an example with clock only:

  • Component A with input port clk mapped in AMBA master bus interface m
  • Component B with input port clk mapped in AMBA slave bus interface s
  • Design with instance a of component A and instance b of component B and interconnection from a.m to b.s

If you netlist the design you will a get a net between a.clk and b.clk but this net is not driven since both ends of the net are inputs. Now lets assume you also have

  • Component C (clock generator) with output port clk mapped in CLOCK master bus interface clock.

As integrator, you can now make an integration specific phantom component and change the design as follows:

  • Component I with phantom port clk that is mapped in three three bus interfaces
    • CLOCK slave bus interface clock
    • AMBA slave bus interface s
    • AMBA master bus interface m
  • Design as before with the interconnection and additional instance c of Component C and instance i of Component I and interconnections
    • a.m to i.s
    • i.m to b.s
    • c.clock to i.clock

If you now netlist this design you will get a net between c.clk (driver) and a.clk and b.clk. Instance i will not appear in the netlist as a module instance since it only has phantom ports.

In my opinion, the use of a phantom component is the cleanest way to do this. Alternative ways are to connect c.clk via an adhoc connection to a.clk and/or b.clk, or to add additional clock slave interfaces to A or B such that you can connect c.clock to those interfaces. However, you then add additional interfaces only for integration purposes.

There is an example in the user guide ( https://accellera.org/images/downloads/standards/ip-xact/IP-XACT_User_Guide_2018-02-16.pdf ) of a phantom component for I2S. You can make similar components for AMBA protocols and other Serial protocols.

Best regards,
Erwin

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Hi Erwin

Thanks for the explanation. It clears a lot of doubts. I really appreciate your efforts.

I have one more related questions. If I have a component with I2C master interface and another component with I2C slave interfaces. As I2C interface is asymetric, so I cannot connect master to slave directly. In this case how these two component can be connected. Do we need some extra abstractor/bridge or phantom component with mirrored interfaces here to make the connections ?

Thanks

Khushi

 

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Hi Kushi,

The Accellera bus definitions contains files for I2C. There are two: one for I2C internal (uni-directional signals) and one for I2C external (bidirectional signals). They allow you to make direct connections from master to slave. A bus does not have to be symmetric to support direction connections. The bus definition property directConnection determines if you are allowed to make direct master to slave connections or not.

Best regards,
Erwin

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