David Black

Consider using a uvm_event from the uvm_event pool and possibly a uvm_event_callback. Monitor 1 sends a delayed event: task monitor1::run_phase( uvm_phase phase); My_transaction sent_txn; uvm_event sent_evt = uvm_event_pool::get_global_pool().get("my_timed_event"); uvm_event rcvd_evt = uvm_event_pool::get_global_pool().get("my_received_event"); forever begin ... collect transaction ... timeout: fork begin received_evt.wait_trigger(); disable timeout; #timeout evt.trigger( sent_txn ); join_none end endtask: monitor1 Monitor 2 sends received transaction: task monitor2::run_phase( uvm_phase phase); My_transaction rcvd_txn; uvm_event rcvd_evt = uvm_event_pool::get_global_pool().get("my_received_event"); forever begin ... collect transaction ... rcvd_evt.trigger( rcvd_txn ); ... end endtask: monitor2 Scoreboard waits for either: task My_scoreboard::run_phase(uvm_phase); My_transaction txn; uvm_event sent_evt = uvm_event_pool::get_global_pool().get("my_timed_event"); uvm_event rcvd_evt = uvm_event_pool::get_global_pool().get("my_received_event"); forever begin bit timeout = 0; get_data: fork timed_out: begin sent_evt.wait_trigger(); $cast( txn, sent_evt.get_trigger_data() ); timeout = 1; disable received; end received: begin rcvd_evt.wait_trigger(); $cast( txn, rcvd_evt.get_trigger_data() ); disable timed_out; end join_any ... end endtask: My_scoreboard::run_phase You might need the callback to disable an event in flight.

I think you are slicing the data structure. See https://stackoverflow.com/questions/274626/what-is-object-slicing.

sc_core::wait will always move to a subsequent (i.e., different) delta cycle. // sc_time_stamp: 0 s sc_delta_count:0 wait( 1, SC_US ); // sc_time_stamp: 1 us sc_delta_count:1 wait( SC_ZERO_TIME ); // sc_time_stamp: 1 us sc_delta_count: 2 wait( 2, SC_NS ); // sc_time_stamp: 1002 ns sc_delta_count: 3

I would further suggest that the static casting sounds suspicious, but without actual code we cannot determine much about the situation. Ideally you could put a subset of your code on www.EDAplayground.com and share a link. You might also consider turning on compiler switches such as GCC’s --pedantic and -Wall to see if the are any coding violations.

Probably because LeakSanitizer was designed with a proper understanding of pthreads; whereas, the non-pthreads implementation uses Q(uick)Threads (or some variant), which implements some assembly language to play with the processor stack to perform context switching. This confuses most if not all memory analysis programs. Pthreads is more universal but slightly slower than QThreads.

uvm_config_db is simply a facade pattern on top of the uvm_resource_db. As mentioned above, most recommend avoiding direct use of the resource db because the config db adds more consistency to its use.

The simple answer is that SystemC does not know how to trace std::string, and much less and array of std::string. First, std::string is a dynamically variable array of characters, which will perplex waveform viewing because you need a fixed number of signals to display. Changing to a fixed std::array<char,10> would help. You would still need to write an overload something like: template<int depth> void sc_trace( sc_trace_file* tf, const std::array<char,depth>& A, const std::string& name ) { // Code to trace individual char's for(int i=0; i<depth; ++i) { string elt_name = name + "["s + to_string(i) + "]s"; //< using modern C++14 sc_trace( tf, A[i], elt_name ); } } Even a simple array of int would need an overload.

You’re only allowed to call sc_trace one time for each variable and after that tracing is automatic. So you need to move the sc_trace calls out into the constructor or into end_of_elaboration or somewhere else before simulation starts. You also need to move your local variables in to the class as members.

Compile checks are to ensure that you are using the same version of GCC and SystemC and flags to build the code as was used to compile the library. Everything needs to use the same tool/library set. This includes the version of the C++ standard you are using (suggest C++14 or better).

Yes, but it will depend on whether you have a simulator that is licensed for coast simulation. Simply be sure to follow the instructions provided by the simulation vendor (E.G, Synopsys or Cadence, etc.).

Code itself looks fine. I ran the above on EDAplayground without problem. I also ran on MacOS 10.15.7 (Catalina) with Apple clang++ 12.0 (LLVM ) Here is a link to where I ran it: https://edaplayground.com/x/V25h SystemC 2.3.3-Accellera --- Sep 21 2020 10:55:34g++ 7.5Using C++ standard 201402Ubuntu 18.04 You might consider upgrading g++ (4.8 is pretty old). I use g++ 9.3 normally.

SystemC is a discrete event driven simulator using an approach similar to Verilog, SystemVerilog and VHDL.The coding approach assumes cooperative multitasking. This is very time efficient and more importantly simplifies the modeling aspect if you really understand it, and makes it easier to interoperate with other simulators. Immediate notification is a unique feature of SystemC that works for some models, but not all. The reasoning behind it is simple efficiency. Delayed notification (i.e., SC_ZERO_TIME) is the safest approach if you are not certain that other processes are designed to work with immediate notification. Both potentially (likely) result in additional delta cycles. I have an old presentation (with code) that graphically single steps the simulator to make its behavior easier to understand under https://github.com/dcblack/SystemC-Engine/.

@plafrattTLM2 is built to allow any protocols you like. The "base protocol" was deemed sufficient for most needs; however, TLM2 was designed specifically to allow alternatives. Furthermore, the standard provides mechanisms to keep the cost of adapters/bridges between protocols simulation efficient. [Plug - ignore if you like] The Doulos course on TLM 2.0 <https://www.doulos.com/training/systemc-tlm-20/systemc-modeling-using-tlm-20-online/> investigates the base protocol and then builds up to a module describing custom protocols.

There are several ways to approach this. A custom channel would be another approach, where the channel determined connectivity internally. I would also say that these approaches would not be considered "hacky". SystemC is intentionally built on C++ [see note] to allow you more freedom in modeling. Synthesis tools are a bit more picky, but for modeling there are many approaches. Usually, it helps to provide block diagrams describing what you are modeling and where the connectivity needs to be dynamic. From that we can make a number of suggestions. A hack approach would involve modifying the SystemC source code itself directly. That I would strongly discourage. You may look at it and even copy ideas from it, but don't use a modified SystemC source except experimentally when proposing changes via a git branch (and you probably need to be a committee member). Note: The best modeling teams develop strong C++ proficiency (i.e., go beyond the basics of C and really learn a solid breadth of coding techniques in C++ using the full standard library).

sc_port's and their derivatives are not designed to be changed after elaboration. You could use multiports and simply change which index you are using. If needed you could create a wrapper to encapsulate the issue.

No. sc_clock models a fixed period clock with an optional start delay. If you want to model a clock that can be changed, it is simple enough to model yourself. You can use sc_signal_if<T> as the basic interface and add to it from there. For example, I have modeled a no_clock as you can see https://github.com/dcblack/no_clock.

Analysis ports are non-blocking by definition. Subscribers are required by the standard to: Not do any blocking activities (e.g. wait()) Not to modify any aspects of delivered reference. Copy the payload if you want to extend the lifetime of the payload

You should call sc_stop exactly once. Then you won’t get any errors.

I believe the original User Guide was removed; however, there are plenty of resources: There are many proper examples with documentation (PowerPoint or Markdown or README.txt) inside the Proof of Concept download package (obtain from https://accellera.org/images/downloads/standards/systemc/systemc-2.3.3.tar.gz) Books such as SystemC: From the Ground Up 2nd Edition (myself et al), SystemC Methodologies and Applications (Muller et al) The standard itself is fairly readable (obtain free from https://ieeexplore.ieee.org/document/6134619) Somewhat more important for many is C++ itself. SystemC describes a methodology and a class library for modeling written in C++. As such, many users struggle with basic syntax because they do not have proficiency in C++. SystemC can be used with C++17; although, many continue to struggle with the old C++98 standard. Currently, I work as an instructor at Doulos. If you would like formal training for a quick ramp, please consider checking us out: https://www.doulos.com

Yes, interleaving is possible in such cases the delays can be modeled but you will likely want to add some type of protocol extension (e.g., to track the transaction id when breaking up a response) and likely need to create a custom protocol as defined by the standard. The four timing points of TLM 2.0 are meant to define a basic starting point for protocols. You can also update timing in the interconnect and even deal with arbitration issues by splitting up transactions, but this is not typically done. Of course if you have a custom protocol, there are implications to interoperability and you may need to design/implement protocol adapters. Keep in mind that TLM models are generally cycle-approximate and not cycle by cycle accurate. This is because SystemC is trying to provide timing information sufficient for architectural exploration, which generally only needs to be 60% to 80% accurate. RTL accuracy should be left for the RTL; otherwise, your SystemC model complexity might slow down development and execution to the point where it was meaningless. Ideally, SystemC models are designed to execute many times faster than RTL simulations, but still give us "sufficient" information to make architectural analysis possible.

What version of SystemC do you have? Did you compile SystemC with the same versions?

I think it is simpler than you think. Just set the data length to reflect the size of the burst. In the target you can set the latency to reflect the burst size based on socket width and byte enables if used. Sure you wont see the timing of the burst internals but unless your bus protocol allows intra-burst interlehaving, this should not be a problem. Remember that TLM is only cycle approximate. This provides faster simulations that are reasonably accurate. Example: socket width 16 bits, transfer length of 32 bits. Obviously takes two clocks.

@eyck nailed it.

The syntax of SystemC is C++. C++ supports float, double, and long double. The basic idea of SystemC is to raise abstraction above (away-from) RTL to obtain faster running simulations. So modeling a pipelined multiplier can be quite trivial using three SystemC processes: Grab inputs and schedule to be placed into pipeline on the next clock using sc_event. Schedule an sc_event_queue for stages*clock_period and place calculation into queue. When event queue triggers, pop the queue and output the value. If you need to deal with floating point status, that can be placed in the queue as well at the point of computation and updated when it pops out.

SystemC FIFO's represent hardware and as such may only be created during construction of a model. After elaboration closes, you are not allowed to add more fifos. None of your code examples above are complete, so it is fairly hard to give you a complete answer. Perhaps you could put your design on https://edaplayground.com and share a link with us. For details on phases of SystemC (e.g. elaboration) see IEEE-1666-2011.pdf, which you can obtain through Accellera.org.