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iamgame

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  1. 1. Cluster – Is a module, which hosts various compute elements, and multiple arrays of DMEs. In this block diagram two DME-Array – each comprising of 4 DMEs is shown. Cluster is connected to multiple NoCs. Each DME-Array is connected to a NoC based on memory type that the array hosts. 2. DME – Dma and memory element. One DME differs from another in terms of size/banks, security and power characteristics (voltage, and power states) of its memory. There are specific NoC to connect DME-Arrays with specific mem type. There could be multiple NoCs, each connecting common MemType DM arrays. Two
  2. Hi David, Please find the block diagram attached. The textual description that goes with the pic, is in subsequent message. Thanks.
  3. Hi David, Thanks for your response. I will draw a pic and try to highlight the need. Apologize the delay. Thanks.
  4. Hi David, Thanks for you time and response. 1. If I use initializer list of constructor, I would be initializing the socket (a static variable) multiple times. I am looking to design the code in such a way that multiple instances of my_module will all same same socket to send/receive their request. 2. I do not understand uniform initialization syntax. After I declare static tlm_utils::simple_target_socket<my_module> socket; in the definition of class my_module and define the static variable in my source file as tlm_utils::simple_target_socket<my_module>
  5. Hi All, Is it possible to have simple_target_socket as static member of a module ? It needs to defined outside the class, can we define and initialize it in constructor ? // header class my_module : public sc_core::sc_module { public: my_module(sc_module_name name); static bool isSockettInitialized_; static tlm_utils::simple_target_socket<my_module> socket_; }; // source file //instantiate socket, cannot initialize it, because it is outside sc_module - it would throw and E100 error. tlm_utils::simple_target_socket<my_module> my_module::s
  6. Hi All, I coded up (in TLM) few modules for my SoC (cache mem, interconnects, dma engines etc). I have mostly used simple_initiator_socket and simple_target_sockets for all of my SoC components. I'm modelling for cycle accurate comparison with RTL. My aim is to correlate model with RTL design - in terms of cycles consumed, peak/avg bandwidth/latencies at internal and external memories. What is best way to extract, log and aggregate this information ? Is accumulating delays and time info across API calls like simple_initiator_socket::nb_transport_fw/bw() best way to do it ? Are there TL
  7. Thanks Eyck. I guess I forgot to add important detail. Class ExistingDesignBase as mentioned in first version - is base for every module in design. There are about 40 modules in the design. And the top level class TlmModule, has few modules inside it. Could this lead up to any issue to sc_module hierarchy ? I observed that this message is thrown from sc_port.cpp if the check for parent of sc_module fails. Thanks
  8. Hi All, I am modifying an existing functional model for my hardware to make it cycle accurate. I get aforesaid error, for my slightly longer hierarchy of classes. class Port { tlm_utils::simple_target_socket<Port> socket_; } class Memory { Port *port; } class TlmMemory::public ExistingMemory{ Memory *mem; } class TlmModule :: public ExistingModule { TlmModule(sc_module_name nm); //socket connection is done here. tlm_utils::simple_initiator_socket<TlmModule> socket_; TlmMemory *tlmMem; } class ExistingModule :: public ExistingModuleBase
  9. Dear TLM Experts, Could someone please shed some light on this ? I have been able to create a transactionID using extension in GP. In order to trace how each transaction is progressing in my system, I am thinking of using transport_dbg API of sockets, such that every time a socket sends or receives a Tx - it will get logged. Would this be right / clean way of logging every Tx ? I am not clear yet about who would call transport_dbg (with in socket class) after I register a callback for transport_dbg ? Also when is transport_dbg called when Tx travels via non blocking interfaces of an init
  10. Hi All Basically for debugging purpose I want to trace every transaction (Tx) going around in my model. I would like to assign an ID to each Tx so that it becomes easy to trace them. I have following questions in this context. I am in early stages of using TLM . 1. What is best way to annotate each Tx ? a) I am thinking of using extensions in generic payload - following ./tlm-2/examples/lock_example.cpp b) Could there be some generic TLM classes in open source that people developed for this specific purpose ? I am thinking of wrappers around core gp,
  11. Hi SC/TLM experts, I have same question/need. Could someone please enlighten ? Are there examples which illustrates usage of gp extensions ? Thanks.
  12. Hi Eyck, Thanks for your replay and help. Will reach out. Thanks.
  13. Hi Folks, Are there good open source libraries out there to model (AT/FT style) SoC components (memories, buses, simple nocs, dma engines, registers which can be decoded off of APB) ? Upon some searching I came across - 1. scml/scml2 - https://gitlab.larc-nthu.net/rgly/scml/-/tree/6cb6356704245b9c17f816ba957f1a0971d76a67 (does not offer bus components) 2. System C components - https://github.com/Minres/SystemC-Components (offers bus components - but the buses do not seem to have non block transfer interface) 3. VCML - https://github.com/janweinstock/vcml (offers bus compon
  14. Thanks for your response and help David.I was particularly indecisive about #2. I am designing solution along lines of your suggestion in #3. Will design a 'MemPort' class which implement 4 phase base protocol using simple_target_socket_tagged<>, and array of n such port objects will be instantiated in parent class called 'Memory'. Thus every port's socket would invoke 'arbiter' (a member function in parent Memory class ), upon receiving a Tx at the port (as response to BEGIN_REQ phase). Question 7 : The arbiter decides the priority of Tx based on Port ID. So Tx from 0, 1, 2 .
  15. Hi All, I am looking to model SRAM (SC_MODULE (memory) ) which has n Rd and m Wr ports. It has multiple banks. Transaction from ports need to be arbitrated for bank conflicts. 1. What is best way to model multiple ports ? Would it be clean to use list / vector of simple_target_socket_tagged <> ? 2. Would having a 'router' between (n+m) ports and banks make for cleaner class design ? 3. If we take up simple port based design as opposed to using a router - what would be best way to manage 4 phase socket communication protocol ? 3. Do we need to pay attention to
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