David Black

You’re only allowed to call sc_trace one time for each variable and after that tracing is automatic. So you need to move the sc_trace calls out into the constructor or into end_of_elaboration or somewhere else before simulation starts. You also need to move your local variables in to the class as members.

Compile checks are to ensure that you are using the same version of GCC and SystemC and flags to build the code as was used to compile the library. Everything needs to use the same tool/library set. This includes the version of the C++ standard you are using (suggest C++14 or better).

Yes, but it will depend on whether you have a simulator that is licensed for coast simulation. Simply be sure to follow the instructions provided by the simulation vendor (E.G, Synopsys or Cadence, etc.).

Code itself looks fine. I ran the above on EDAplayground without problem. I also ran on MacOS 10.15.7 (Catalina) with Apple clang++ 12.0 (LLVM ) Here is a link to where I ran it: https://edaplayground.com/x/V25h SystemC 2.3.3-Accellera --- Sep 21 2020 10:55:34g++ 7.5Using C++ standard 201402Ubuntu 18.04 You might consider upgrading g++ (4.8 is pretty old). I use g++ 9.3 normally.

SystemC is a discrete event driven simulator using an approach similar to Verilog, SystemVerilog and VHDL.The coding approach assumes cooperative multitasking. This is very time efficient and more importantly simplifies the modeling aspect if you really understand it, and makes it easier to interoperate with other simulators. Immediate notification is a unique feature of SystemC that works for some models, but not all. The reasoning behind it is simple efficiency. Delayed notification (i.e., SC_ZERO_TIME) is the safest approach if you are not certain that other processes are designed to w

@plafrattTLM2 is built to allow any protocols you like. The "base protocol" was deemed sufficient for most needs; however, TLM2 was designed specifically to allow alternatives. Furthermore, the standard provides mechanisms to keep the cost of adapters/bridges between protocols simulation efficient. [Plug - ignore if you like] The Doulos course on TLM 2.0 <https://www.doulos.com/training/systemc-tlm-20/systemc-modeling-using-tlm-20-online/> investigates the base protocol and then builds up to a module describing custom protocols.

There are several ways to approach this. A custom channel would be another approach, where the channel determined connectivity internally. I would also say that these approaches would not be considered "hacky". SystemC is intentionally built on C++ [see note] to allow you more freedom in modeling. Synthesis tools are a bit more picky, but for modeling there are many approaches. Usually, it helps to provide block diagrams describing what you are modeling and where the connectivity needs to be dynamic. From that we can make a number of suggestions. A hack approach would involve modifyi

sc_port's and their derivatives are not designed to be changed after elaboration. You could use multiports and simply change which index you are using. If needed you could create a wrapper to encapsulate the issue.

No. sc_clock models a fixed period clock with an optional start delay. If you want to model a clock that can be changed, it is simple enough to model yourself. You can use sc_signal_if<T> as the basic interface and add to it from there. For example, I have modeled a no_clock as you can see https://github.com/dcblack/no_clock.

Analysis ports are non-blocking by definition. Subscribers are required by the standard to: Not do any blocking activities (e.g. wait()) Not to modify any aspects of delivered reference. Copy the payload if you want to extend the lifetime of the payload

You should call sc_stop exactly once. Then you won’t get any errors.

I believe the original User Guide was removed; however, there are plenty of resources: There are many proper examples with documentation (PowerPoint or Markdown or README.txt) inside the Proof of Concept download package (obtain from https://accellera.org/images/downloads/standards/systemc/systemc-2.3.3.tar.gz) Books such as SystemC: From the Ground Up 2nd Edition (myself et al), SystemC Methodologies and Applications (Muller et al) The standard itself is fairly readable (obtain free from https://ieeexplore.ieee.org/document/6134619) Somewhat more important for many is C+

Yes, interleaving is possible in such cases the delays can be modeled but you will likely want to add some type of protocol extension (e.g., to track the transaction id when breaking up a response) and likely need to create a custom protocol as defined by the standard. The four timing points of TLM 2.0 are meant to define a basic starting point for protocols. You can also update timing in the interconnect and even deal with arbitration issues by splitting up transactions, but this is not typically done. Of course if you have a custom protocol, there are implications to interoperability and you

What version of SystemC do you have? Did you compile SystemC with the same versions?

I think it is simpler than you think. Just set the data length to reflect the size of the burst. In the target you can set the latency to reflect the burst size based on socket width and byte enables if used. Sure you wont see the timing of the burst internals but unless your bus protocol allows intra-burst interlehaving, this should not be a problem. Remember that TLM is only cycle approximate. This provides faster simulations that are reasonably accurate. Example: socket width 16 bits, transfer length of 32 bits. Obviously takes two clocks.

@eyck nailed it.

The syntax of SystemC is C++. C++ supports float, double, and long double. The basic idea of SystemC is to raise abstraction above (away-from) RTL to obtain faster running simulations. So modeling a pipelined multiplier can be quite trivial using three SystemC processes: Grab inputs and schedule to be placed into pipeline on the next clock using sc_event. Schedule an sc_event_queue for stages*clock_period and place calculation into queue. When event queue triggers, pop the queue and output the value. If you need to deal with floating point status, that can be placed in th

SystemC FIFO's represent hardware and as such may only be created during construction of a model. After elaboration closes, you are not allowed to add more fifos. None of your code examples above are complete, so it is fairly hard to give you a complete answer. Perhaps you could put your design on https://edaplayground.com and share a link with us. For details on phases of SystemC (e.g. elaboration) see IEEE-1666-2011.pdf, which you can obtain through Accellera.org.

Usually, we compile the client code to run on a simulated processor, usually known as an ISS (Instruction Set Simulator). This will give you the correct behavior. The ISS will call wait periodically and thus do what you desire. One other possibility that I hesitate to suggest is to run your system code in a separate OS thread (not a SystemC thread) and then interact with it via proper thread-safe semantics (probably using a custom primitive channel utilizing asyc_request_update). I can reasonably expect this will not provide satisfactory results because it will not provide the proper timi

In a cooperative multitasking environment (e.g. SystemC), it is impossible to have an infinite loop without yielding. The only yielding method available in SystemC threads is the wait() method; therefore, you have self-defined an impossible problem. SystemC processes (SC_THREAD and SC_METHOD) are NOT the same concept as OS processes or threads. They are constructs of the discrete event driven simulator known as SystemC. Now it is possible in some cases to trick the code, which I have used for some cases. For example, if your FW_main code where to attempt some I/O with a common method

Be very careful with terminology here. If you are asking about host simulator OS threads, the answer is pretty much no. SystemC is a discrete event driven simulator using cooperative multitasking (which greatly simplifies coding) and is not thread safe. You might want to look at what is contributing to the slowdown. You should probably use a software profiler. There are two issues that commonly cause problems in SystemC: I/O. More specifically output to the log file. If your simulation has lots of SC_REPORT_INFO or std::cout producing large logs at run-time, then you will defin

I don't know where you got that specification, but it looks suspiciously like a university project. Also, whoever is using the word 'static' is not using the word correctly. Nor would or should that approach ever work. The diagram implies a hierarchy of SystemC modules with a cluster module containing several DME-array modules, which in turn contain DME, DMA and MemType2 modules. These could of course be modeled without the illustrated boundaries, but it would add unnecessary complication. The outermost module (Cluster module) would have one each of an initiator and target TLM-2.0 socket (NOT

Nothing wrong. Your output will be available after the delta cycle completes. You can view the new value in the next delta cycle. The problem for you conceptually is that you think 'S_val_out = expression' is a blocking statement. In other words, you expect the value to be transferred to the current value of S_val_out at the end of the assignment. Actually what is happening is akin to: S_val_out->write( A_val_in->read() +B_val_in->read() ); External to your sum class object, the S_val_out is bound to a channel sc_signal<T>, where the write() method is implemented. T

No problem. Glad you got what you needed. For what it's worth, the return value from system calls is generally 0, 1 or 256. Believe I read somewhere that values above 256 are reserved for OS. 0 means success, and all others mean failure. I generally return 1 to indicate "errors detected while running".

Yes and no. SystemC ports (e.g., sc_port<T>) sit on the boundary of a SystemC module to allow communication with external channels. They point outward from a module towards the channel. SystemC exports point inward towards a channel within the module or within submodules via additional export. sc_in<T> is a partial template specialization of sc_port using an sc_signal_in_if<T>. So the answer to your question depends on where the ports are located vs. the module and channel. A picture would help. What books on SystemC have your read?