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TonyJ's Achievements


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  1. Yep....100% on everything you said. I have actually tagged the data. The race condition is actually the very thing I am banking on. I want the flow of these descriptors to truly be interleaved in a non-deterministic manner, as this more accurately mimics actual HW behavior. If the users of what I'm building require tighter control, then they can manage it with say a higher level v-sequence that manages each of the attached clients generating said descriptors.
  2. Rookie question: Is it as obvious as it may seem to simply have just the one imp on the consumer side of say a put_port (non-blocking most likely), and multiple producers can connect to that single imp? Yes, they would all be the same item types, and yes they would all be handled the same way. Not the same as an analysis_port. More like an analysis_port with the traffic flowing the opposite direction. Any issues I may be overlooking or missing?
  3. DUH! was thinking too hard. Couldn't see the forest through the trees. Thanks!!
  4. Is there a way for a virtual sequence to pass a sequence_item (that it has already created) to a sub-sequence, say for instance to an agent sequence, without using a TLM? I really would like to avoid adding a TLM to the agents sequencer if I can avoid it. The sub-sequence would be invoked from the v-sequence by calling start(). The sequence_item is a potentially largish data structure so using the `uvm_do_on_with macro is a bit unwieldy. I think I see a sneeky way to do it by using the parents mid_do() method, but haven't tried it yet and wondering if there's a more direct way I'm not seeing. Thanks in advance.
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