uwes

hi, transaction recording into a gui requires auxillary support delived by your simulator vendor. the uvm-accellera distribution only has textual output.to see the transactions in simvision try the following: irun -uvm -gui +uvm_set_config_int="*“,recording_detail,1 ... <rest of vlog....> then run for some time, then you have in the design browser an additional hierarchy holding all transaction streams you can now select and push into the waveform/sequence chart etc. /uwe

since this appears to be a generic crash it would be good if you file a bug report with cadence support. the issue might be related to uvm or to the other code you have - but anyway r&d needs to look at it. /uwe

this only happens if you compile in the old 3step mode (ncvlog/ncelab/ncsim) and you miss to supply the shared libraries (either the precompiled libuvmdpi.so, libuvmpli.so) or if you compile the dpi code yourself and forgot the -sv_lib ..../yourlib.so (btw the right set of switches are in another post here in the forum, search for "loadpli") much simpler is the invocation using "irun -uvmhome <your-uvm> ...." /uwe

since uvm is an superset of ovm there is a upgrade path from ovm to uvm (hope the original poster flipped the sides). there is even script for that which does most of the things. going from uvm to ovm (well - why first of all) can only be done if you use none of the uvm-additional stuff

pretty hard to tell without more info but its good to validate things step by step 1. all components instantiated 2. all components build 3. invoking .super() in all _phase() fiunctions/tasks 4. running in active mode (so sequencers are built) 5. right sequence configured? 6. is the right sequence selected? (check the messages talking about default-sequence) 7. starting the sequence manually? is the code started 8. which phase is used for the sequence? 9 is the phase protected from ending using objections? 10. is the expected printout in a function/task which really gets executed (pre_body is only executed for root sequences) 11... /uwe

hi, you could create a combined operation 1. write frontdoor first 2. using the custom backdoor you could wait upon the change (wait_for_change) 3. once the change passed you read via the backdoor and check /uwe

read carefully what the message says (does the virtual sequence run on this virtual sequencer (are they compatible?) OR does that happen when the virtual sequencer sends a real sequence to a lower layer sequencer? (validate that its the right kind of sequence for the sequencer)? do the sequencers/sequences/sequence items involve paramters? if so check all elements are compatible ? typically the easiest path is to stop in your sequence/sequencer and look at the generated sequence and the sequencer and determine if the types are compatible and as expected /uwe

well, it just means that VCS isnt compatible with the vhpi header file/api used to access vhdl signals in $UVM_RGM_HOME/dpi/rgm_set_hdl.c. the options are simulator dependent

are you using rgm with VHDL (as DUT)? if not you might want to define RGM_NO_VHPI during c code compile

hi, everything started from the xyz_phase() callbacks is terminated at the end of xyz_phase(). if you want to take control over the thread management you have to hook into the phase_started() and phase_ended() callbacks. in there you can check if pre_main_phase is starting in order to start your own thread. please note that in case of jumps you might invoke pre_main_phase multiple times. /uwe

if you are starting new, don't have other dependencies as outlined before and the UVM_REG feature set matches then UVM_REG is the THE choice.

and remove the INCA_libs directory. i assume the old stuff is still in there /uwe

hi, yes, as kathleen suggested remove the "include uvm_pkg" and either put it on the cmdline or use simply "-uvm" which does that under the covers.

hi, this is a general principle in UVM that clone/copy is not performed by default (since this costs). if an object wants to keep a "private"/"unchangable"/persistant copy of an object it has to perform the copy/clone itself. in your example you either allocate a new transaction all the time and pass this new object around OR you allocate it once (outside of the repeat) and have everyone who needs a private/persistant copy to perform the clone/copy. /uwe

this sounds like http://eda.org/svdb/view.php?id=3369

hi, you should be looking at the uvm_reg_backdoor's auto-update capability (see uvm_reg_backdoor::is_auto_updated. a very simple impl. is attached class my_bkdr extends uvm_reg_backdoor; function new(string name = ""); super.new(name); endfunction task read(uvm_reg_item rw); do_pre_read(rw); rw.value = new[1]; rw.value[0] = dut.register; rw.status= UVM_IS_OK; do_post_read(rw); `uvm_info("BKDR","performed read",UVM_HIGH) endtask task write(uvm_reg_item rw); do_pre_write(rw); dut.register = rw.value[0]; do_post_write(rw); `uvm_info("BKDR","performed write",UVM_HIGH) endtask virtual local task wait_for_change(uvm_object element); @(dut.register); `uvm_info("BKDR","detected change",UVM_HIGH) endtask function bit is_auto_updated(uvm_reg_field field); return 1; endfunction endclass

hi, you can use the extension mechanism during read/write. simply supply an own property container in the .extension arg. this is later avail in uvm_reg_item.extension in the uvm_reg_adapter /uwe

hi, you should be using 10.20s100+, 11.x or a 12.x version. older versions have known issues leading to INTERRs such as the one in the log. /uwe

hi, typically you should be using just "irun -uvmhome <your-uvm-lib> ....rest-of-args...." and remove any incdirs/uvmpkg compile/dpi compile from the commandline. i assume you were using your own compile without any "-uvm/-uvmhome" switch and not adding the dpi c files to the compile. to cross check post your compile/elab/run invocation /uwe

hi, this is more a "design methodology / rules" question. there are safe design rules which basically ensure that you dont have race conditions, your rtl behaves like the synth netlist, you are not using "grey" LRM constructs/semantic,... Since these are lots of rules people typically use design-rule checker, linter etc. you may even run on different simulators to spot suspicious behavior and see if simA and simB have a common understanding of what you described. /uwe

hi, i dont think its per se a bug in the uvm library since there is no objection with the name "build". i assume that "build" is a user objection and for some reason you are dropping more objections than you have raised before. /uwe

hi, you dont need to cast from child to parent at all since a derived is always a base. you can directly assign a derived class handle to a base class handle. the reverse is not always true therefore you need to check at runtime. not necessarily, have a look at the attached code module test193; virtual class car; endclass class mercedes extends car; endclass class renault extends car; endclass car c; mercedes m; renault r; initial begin m=new(); // this is not needed since a "mercedes" is always a "car" void'($cast(c,m)); // do the previous the simple way c=m; // the reverse needs a cast since a "car" is not necessarily a "mercedes" r = new(); c=r; assert($cast(m,c)); //this should fail c=m; assert($cast(m,c)); // this should pass end endmodule

hi, a minor side comment: 1. get rid of ANY "include something of uvm" and replace this with "import uvm_pkg::*;" 2. add "`include uvm_macros.svh" as necessary 3. either add the uvm_pkg.sv file to your list of files to compile OR in the case of ius have irun take care of the compilation using the -uvmhome switch 1-3 will most likely not solve your issue BUT it prevents you from other errors down the road /uwe

putting a queue/da into the db should work if the simulator supports it module test189; import uvm_pkg::*; typedef int qda[$]; initial begin qda b = '{1,2,3,4,5}; uvm_config_db#(qda)::set(null,"path","field",; end endmodule if the simulator does not support it directly you may still wrap it into a container class..

if possible please open a service request with cadence support along with your compile invocation arguments. could it be that you try to run with an own uvm library?