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myskan

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About myskan

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  • Birthday 02/13/1978

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  1. Hi, I'am UVM starter and I did download UVM example on the website (http://www.testbench.in/UT_02_UVM_TESTBENCH.html) (http://www.testbench.in/uvm_phases.tar) I did not change example except 2 parts below 1. in the top.vs `include "uvm.svh" -> `include "uvm.sv" 2. in the Makefile irun ${UVM_FLAGS} +incdir+. ${FILES} +UVM_TESTNAME=test1 -> irun -uvmhome $(UVM_HOME) ${UVM_FLAGS} +incdir+. ${FILES} +UVM_TESTNAME=test1 After $> Make ius the simulation time is 0 like thie Simulation complete via $finish(1) at time 0 FS + 186 /net/hw3/work/sclee/my_work/UVM/uvm-1.1a/src/base/uvm_root.svh:408 $finish; Could yo explain why simulation complete time is 0 ? Thanks in advance, Skan, Lee
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