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Hello, Is there a way to generate execution trace for a SystemC project? Thanks, R.Adiga

Hi everyone, my initiator is writing to a specific register but I want to block the initiator if a certain bit of the target register is set (1). is there a way to do that?

Hello All, I am working on SystemC-UVM based testbench. I have created UVM based testbench using UVM code generator. Here I am using three different agents in UVM generator which I have defined as a part of the configuration file which was further being provided to UVM code generator to generate test bench skeleton. And here, in of the agent driver, the code snippet is as: // Drive the inputs of the DUT UVM_INFO(this->name(),"Driving transaction:",0); req.print(); // TODO put your code here But when I try to read the value in my test-case, then I see an error as: And this error is observed inside print() function, once I comment the line "req.print()" from the above snippet the error is no more observed and my test-case runs fine.

Hello, I'm just starting off with TLM-2.0 and would like to explore more about the use cases for byte_enable_ptr. In TLM manual, I see that " A value of 0 shall indicate that that corresponding byte is disabled, and a value of 0xff shall indicate that the corresponding byte is enabled"; Does this mean that we can switch between 0xff and 0x0 if required for every transaction? TLM manual also states that Byte Enable can be used to create burst transfers, can anyone please explain this? Thanks, R.Adiga

Folks, I have requirement to calculate bandwidth per socket. This means I need to count how many transactions were sent on a given socket, and also pass clock information. Are there any example of customizing socket where I can calculate these things and print of at the end of the simulations.

Hi all, im a a student and my project is about systemC, im searching for a freelancer who can help please send to me a private message. thank you

hi all, i want to integrate systemC and openCv in visual studio 2015 to process images for motion detector system. it is possible to do that ? thanks

SOLVED: Nevermind, I made some mistakes in calling the wrong methods for writing/reading from ports. Thanks for your attention anyway! I'm trying to implement this example of a memory and a cpu that are communicating. CPU <==> MEM The modules use a single bidirectional data-line for reading/writing. I defined a signal in sc_main: sc_signal<int,SC_MANY_WRITERS> s_memdata; which I connect to the CPU and MEM module through their ports: sc_inout<int> p_memdata; The CPU is writing to the s_memdata signal: p_memdata.write(getrnddata()); As well as the memory: p_data.write( m_data[ m_curAddr ] ); In the debugger I see that the m_curAddr is changing correctly. Yet, the VCD file shows that the signal "data" is not changing when the "address" is changed (as shown in the figure) Actually, the "data" only changes when the cpu is writing to it, not when the memory is. (I was not able to show the function read/write signal because the enum didn't show in the VCD file). It seems to me that there is something going on with the two modules writing to the same channel. I've noticed sc_logic that introduces Z and X values, is this the appropriate way? edit: I've created a simple proof of principle with two writers that talk to a single sc_signal< bool, SC_MANY_WRITERS > which seems to work. So the problem is something different. Thanks for any help or tips. mem_tb.cpp int sc_main(int argc, char* args[]){ Memory * mem; CPU * cpu; mem = new Memory("main_memory"); cpu = new CPU("cpu"); /* sgn */ sc_signal<Memory::Function,SC_MANY_WRITERS> s_memfunc; sc_signal<Memory::RETSignal> s_memsig; sc_signal<int> s_memaddr; sc_signal<int,SC_MANY_WRITERS> s_memdata; sc_clock clk; mem->p_addr(s_memaddr); mem->p_func(s_memfunc); mem->p_data(s_memdata); mem->p_sig(s_memsig); cpu->p_memdata(s_memdata); cpu->p_memaddr(s_memaddr); cpu->p_memsig(s_memsig); cpu->p_memfunc(s_memfunc); mem->clk( clk ); cpu->clk( clk ); std::cout << "Running, CTRL+C to exit..." << std::endl; sc_trace_file * trace = sc_create_vcd_trace_file("trace"); sc_trace(trace, s_memaddr, "addr"); sc_trace(trace, s_memdata, "data"); sc_trace(trace, s_memfunc, "func"); sc_trace(trace, s_memsig, "sig"); sc_start(); sc_close_vcd_trace_file( trace ); return 0; } cpu.h #include <systemc.h> #include "memory.h" #include <boost/random.hpp> SC_MODULE( CPU ) { public: sc_in<bool> clk; sc_in<Memory::RETSignal> p_memsig; sc_out<Memory::Function> p_memfunc; sc_out<int> p_memaddr; sc_inout<int> p_memdata; SC_CTOR( CPU ) { SC_METHOD(exec); sensitive << clk.pos(); dont_initialize(); SC_METHOD(done); sensitive << p_memsig; dont_initialize(); m_waitmem = false; rng.seed( time(NULL) ); dist = new boost::random::uniform_int_distribution<>(0,1<<16); } private: boost::random::mt19937 rng; boost::random::uniform_int_distribution<> *dist; bool m_waitmem; int rand(); Memory::Function getrndfunc(); int getrndaddr(); int getrnddata(); void exec(); void done(); }; cpu.cpp Memory::Function CPU::getrndfunc() { switch( rand() % 2 ) { case 0 : { return Memory::FUNC_READ; } default : { return Memory::FUNC_WRITE; } /* 1, and all other cases... */ } } int CPU::getrndaddr() { return rand() % MEM_SIZE; } int CPU::getrnddata() { return rand(); } int CPU::rand() { return (*dist)(rng); } void CPU::exec() { if(m_waitmem) return; int addr = getrndaddr(); Memory::Function f = getrndfunc(); p_memfunc.write(f); p_memaddr.write(addr); if(f==Memory::FUNC_WRITE) p_memdata.write(getrnddata()); } void CPU::done() { if( p_memsig.read() == Memory::RSIG_NONE ) return; m_waitmem = false; p_memfunc.write(Memory::FUNC_NONE); } memory.h #define MEM_SIZE 512 SC_MODULE( Memory ) { public: enum Function { FUNC_NONE = 0, FUNC_READ = 1, FUNC_WRITE = 2 }; enum RETSignal { RSIG_NONE, RSIG_READ_FIN, RSIG_WRITE_FIN, RSIG_ERR }; sc_in<bool> clk; sc_in<Function> p_func; sc_in<int> p_addr; sc_inout<int> p_data; sc_out<RETSignal> p_sig; SC_CTOR( Memory ){ SC_METHOD(execute); sensitive << clk.neg(); m_clkCnt = 0; m_curAddr = 0; m_curData = 0; m_curFunc = Memory::FUNC_NONE; m_data = new int[MEM_SIZE]; m_writesCnt = 0; m_readsCnt = 0; m_errorsCnt = 0; m_errorCode = 0; } ~Memory(); private: int m_clkCnt; int m_curAddr; int m_curData; Function m_curFunc; int* m_data; int m_errorCode; int m_writesCnt; int m_readsCnt; int m_errorsCnt; RETSignal read(); RETSignal write(); void execute(); }; memory.cpp #include "memory.h" Memory::~Memory() { delete[] m_data; } Memory::RETSignal Memory::read() { if( m_errorCode ) { m_errorsCnt++; return RSIG_ERR; } p_data.write( m_data[ m_curAddr ] ); m_readsCnt++; return RSIG_READ_FIN; } Memory::RETSignal Memory::write() { if( m_errorCode ) { m_errorsCnt++; return RSIG_ERR; } m_data[ m_curAddr ] = m_curData; m_writesCnt++; return RSIG_WRITE_FIN; } void Memory::execute() { if( m_curFunc != FUNC_NONE ) { m_clkCnt++; if( m_clkCnt == 100 ) { RETSignal retSig = RSIG_ERR; switch(m_curFunc){ case FUNC_READ : { retSig = read(); break; } case FUNC_WRITE : { retSig = write(); break; } default : { /* */ } } p_sig.write( retSig ); m_clkCnt = 0; m_curFunc = FUNC_NONE; } return; } if( p_func == FUNC_NONE ) return; m_curFunc = p_func.read(); m_curAddr = p_addr.read(); m_curData = p_data.read(); p_sig.write( RSIG_NONE ); }

In my project there are several functions which perform SystemC simulations (each has its own declaration prelude and sc_start()). So they are constructed as follows: // first Simulation: sc_signal<double> s1_sim1; .. ControlFoo<double> *cf = new ControlFoo<double>(); cf->Foo_port(s1_sim1); .. sc_start(); // works fine delete(cf); .. // second Simulation: sc_signal<double> s1_sim2; // this leads to an exception The first simulation runs as desired until the sc_stop(). But when I try to declare new sc_signals after the first simulation is completed then it comes to an exception. How do I solve my problem? Best regards Anne (I also asked this on stackoverflow but no response yet. http://stackoverflow.com/questions/42997196/project-with-multiple-systemc-simulations-leads-to-an-exception)

Hi, i am trying to declare an sc_port from which i want to send a struct (ressource) between two different modules. I declared an interface and a channel to implements the send and receive interface methods but i am experiencing two errors. The first one is C2011 'class ' type redefinition, the second one is C2504 base class undefined. Now the Interface is very simple: //comm_interface.h class comm_send_interface : virtual public sc_interface { public: virtual bool send(ressource) = 0; // send a ressource virtual void reset() = 0; // empty ressource list }; class comm_recv_interface : virtual public sc_interface { public: virtual bool recv(ressource &) = 0; // receive a ressource }; The channel where i implement the methods looks like this: //comm_channel.h #include "comm_interface.h" class comm_channel : public sc_module, public comm_send_interface, public comm_recv_interface { private: ressource rdata[9]; int i; //sc_event send_event, recv_event; public: comm_channel(sc_module_name rc_channel) : sc_module(rc_channel), i(0) {} bool send(ressource r); // write bool recv(ressource & r); // read void reset(); //void register_port(sc_port_base & port_, const char * if_typename_); }; bool comm_channel :: send(ressource r) { if (i < 10) { rdata[i++] = r; //recv_event.notify(); return true; } //wait(send_event); return false; } bool comm_channel :: recv(ressource &r) { if (i > 0) { r = rdata[--i]; return true; //read_event.notify; } return false; } void comm_channel :: reset() { i = 0; } And here i declare the sc_port to send and receive the "ressource". #ifndef ROBOT__H #define ROBOT__H #include "systemc.h" #include "ressource.h" //interface #include "comm_interface.h" struct robot : sc_module { sc_port<comm_recv_interface> rinput; sc_port<comm_send_interface> routput; ressource r; void drill(); void insert(); void tight(); SC_CTOR(robot) { //... }; #endif // ROBOT__H Can you help me with the Problem?! Thanks in advanced!

I created vector of fifos: sc_vector<sc_fifo> fifos; and in my constructor: template <unsigned S> class my_chnl : public my_chnl_if, public sc_channel { sc_vector<sc_fifo> fifos; //vectors of fifos //----------------------------------------------------------- public: //----------------------------------------------------------- //constructor //----------------------------------------------------------- explicit my_chnl(sc_module_name nm, unsigned _size = 4) : sc_channel(nm), fifos("FIFO") { fifos.init(S, _size); } ..... I am getting compile error saying that include/sysc/utils/sc_vector.h:634: error: \u2018c\u2019 cannot be used as a function If I do fifos.init(S), it works, but I get default size of 16. How do I set custom size? Any help? Thanks

Hi there, I'm an engineering student from Venezuela and working on systemC for a class project. I'm having a bad time trying to make a tri-state buffer model on system C. I know there is sc_logic and sc_lv but I just don't know how to work with this two data types. I'm working a project (a microprocessor) and I need to model a tri-state module to hook up with my registers so I'll be able to have control on the data coming out of the registers. In case you wonder here is more info https://www.cs.umd.edu/class/sum2003/cmsc311/Notes/Build/implRegFile.html Any idea on how to model a tri-state buffer module?. thanks in advance.

I'm trying out the example for UVM-Connect 2.3 and I can't get a successful compile. The error message is about the "undefined reference to `m__uvm_report_dpi'. I'm using: GCC 4.5.2 on CentOS 5.11 VCS 2015.09-SP2-3 SystemC 2.3.1 SCV 2.0.0 UVM 1.2 UVMC 2.3.0 Appreciate all the help!

I'm trying out the example for UVM-Connect 2.3 and I can't get a successful compile. The error message is about the "undefined reference to `m__uvm_report_dpi'. I'm using: GCC 4.5.2 on CentOS 5.11 VCS 2015.09-SP2-3 SystemC 2.3.1 SCV 2.0.0 UVM 1.2 UVMC 2.3.0 Appreciate all the help!

Hello All, I want to understand usage of noexcept with SystemC. I read that using noexcept will provide me performance benefits! My doubt is how shall I label a member function noexcept, if it is using a SystemC or a library which throws. Following piece of code is self explanatory and needs assistance on correct usage of noexcept. # ifndef MYNOEXCEPTSCCLASS_H_ # define MYNOEXCEPTSCCLASS_H_ # include <systemc> # include <aLibraryThatThrows> template < typename Tinp , typename Tout > class myNoExceptSCClass : public sc_core::sc_module { private : static Tinp correctVersionForSure() { std::throw "Throwing for fun!" ; } void isThisCorrectVersion1() noexcept { sigOut.write(sigInp.read()); } void isThisCorrectVersion2() { sigOut.write(sigInp.read()); } void isThisCorrectVersion3() noexcept { sigOut.write(aLibraryThatThrows::functionThatThrows()); } void isThisCorrectVersion4() { sigOut.write(aLibraryThatThrows::functionThatThrows()); } public : sc_core::sc_in < Tinp > sigInp ; sc_core::sc_out < Tout > sigOut ; SC_HAS_PROCESS (myNoExceptSCClass) ; explicit myNoExceptSCClass (const sc_core::sc_module_name moduleName_) : sc_core::sc_module (moduleName_) , sigInp ("sigInp") , sigOut ("sigOut") { // Regular Stuffs } ~myNoExceptSCClass() final = default ; myNoExceptSCClass& operator=(const myNoExceptSCClass& other) = delete ; myNoExceptSCClass(const myNoExceptSCClass& other) = delete ; }; # endif Thanks in advance. Regards, Sumit

Hi, I have 2 modules: one Test Bench (TB) and a Device under Test (DUT). The TB has an output port (p_out) to simulate a power on (bool). The DUT has an input multiport (p_in) and inside the DUT there are many modules M with one input port (x_in) connected to (p_in). The idea is to simulate a power on througn TB that is distributed to all internal modules of DUT. Here are the declarations: in TB : sc_out<bool> p_out; In internal moules of DUT: sc_in<bool> x_in; In DUT: sc_port< sc_signal_in_if<bool> , 10, SC_ZERO_OR_MORE_BOUND> p_in; Each time I create an internal modules of DUT, I create automatically a channel of type sc_signal <bool> sig, that I connect between p_in and x_in by doing : sc_signal <bool>* sig = new sc_signal <bool> (); p_in(*sig); x_in(*sig); in main program : sc_signal < bool> sig_power_on; tb->p_out(sig_power_on); I try to connect the signal to the input multiport p_in by : p_in(sig_power_on); But I have the error port cannot be used as a function. Perhaps I don't use the multiport as it would be. Please have you got an idea. Regards

I am new to systemc in ubuntu 14.04 and I am trying to setup up eclipse for a systemc small project. I followed the the provided README in systemc-2.3.1 and the INSTALL to install the library. I then used tutorial here to set up eclipse. The problem is that I have a syntax error tell me that sc_signal_resolved could not be resolved. below is a sample of my code: #include <systemc.h> int sc_main(int argc, char ** argv) { sc_signal_resolved zero, one; // in the rest of the code I will use the zero and one passing them to some gates. return(0); } Please how do I solve this. In Windows with visual studio I have no problem.

Hi all. I'm testing some codes to better understanding tlm. In this moment I have a block with this variable : std::map <tlm::tlm_generic_payload*, unsigned int> queue; Basically a place when I store my transactions using trans pointer as key. This variable is accessed by 2 threads. On as input and one as output. Input is fast, output is slow. Threads Input wait until a location (I check my max size) is free and fill it. In system C I used sc_mutex to check lock and check it every X ns (wait(X,SC_NS)). In tlm I don't want to used fixed time but wait until a location is free. Is there a simple approach to do this or I need to use sc_mutex or similar to share variable among multiple process ? Thanks for every suggestion. I need it!

I am trying to code a very generic module that takes the number of elements of a sc_vector of sc_in from an argument. This module looks like: transformation_arbiter.h using namespace sc_core; using namespace sc_dt; class transformation_arbiter : public sc_module { public: sc_in<bool> clk; sc_vector< sc_in<bool> > enable_in; . . . private: unsigned pre_rep; public: SC_HAS_PROCESS( transformation_arbiter ); transformation_arbiter( sc_module_name trans_arbiter, unsigned ext_pre_rep ): sc_module( trans_arbiter ), pre_rep( ext_pre_rep ), enable_in( "enable_in" ) { SC_THREAD( arbitrate ); sensitive << clk; } void arbitrate() { enable_in.init( pre_rep ); . . . } Then I am instantiating this module, along with a sc_vector of another module (request_generator.cpp) in a top module (top.cpp): request_generator.h . . . using namespace sc_core; using namespace sc_dt; class req_generator : public sc_module { public: //ports: sc_in_clk clk; sc_out<bool> enable_out; . . . top.h #include "trans_arbiter.h" #include "request_generator.h" . . . sc_signal<bool> signal[4]; sc_vector<req_generator> req_gen; transformation_arbiter trans_1_arb; . . . and top.cpp #include top.h top::top(sc_module_name sys_m): sc_module(top_m), trans_1_arb ( "trans_1_arb", 4 ), req_gen( "req_gen", 4) { . . . for ( auto i = 0; i < REQ_MODULES; ++i ) { trans_1_arb.enable_in[i].bind ( signal[i] ); } . . . } The problem is that this causes a segmentation fault in the bind instruction: Program received signal SIGSEGV, Segmentation fault. 0x0000000000412501 in sc_core::sc_vector<sc_core::sc_in<bool> >::operator[] (this=0x7fffffffcec0, i=0) at ./systemc-2.3.1/include/sysc/utils/sc_vector.h:384 384 { return *static_cast<element_type*>( base_type::at(i) ); } If I don't use de delayed initialization of the sc_vector like this: public: SC_HAS_PROCESS( transformation_arbiter ); transformation_arbiter( sc_module_name trans_arbiter ): sc_module( trans_arbiter ), enable_in( "enable_in", 4) { SC_THREAD( arbitrate ); sensitive << clk; } void arbitrate() { . . . } The code works, but then it is not generic anymore, since several instances of the module could have different number of ports, and not always 4. I'd really appreciate any help on this issue. Thanks, Fernando

Hi, I have some situations in my models where I have to write a signal from different drivers. To avoid 'multiple drivers to a signal' error I add SC_MANY_WRITERS flag. Is there any way to allow multiple driers to a signal other than putting above flag? I know about sc_resolved but it works only for sc_logic. whenever i regenerate netlist using tool I had to add the flag manually as the tool doesn't have any way to know its a signal with multiple writers.

I didn't find an efficient bug report entrance so I decided to post it here to see whether people think this is a bug or not. I'm trying to use Ralph's solution to reset the sim context (see http://forums.accellera.org/topic/2273-problem-with-re-instatiation-of-modules/). However, that only works well with those modules that don't have a reset signal. I spent some time debugging this with reset signal and found that: This method, sc_reset::reconcile_resets() at src/sysc/kernelsc_reset.cpp:160, is supposed to iterate over all things in reset_finder_q, a static linked list of sc_reset_finder, and delete sc_reset_finder one by one (see line 168-170 for the nature of a linked list, line 195 for delete). Here comes the bug: after the loop, it should but it forgot to set reset_finder_q to NULL! If reset_finder_q is not NULL when I reset the sim context, the next reset signal at line 97 will append itself to a non-existing queue node, which makes the next reconcile_reset cast seg fault. I could see that it's indeed undefined behavior to reset the sim context, but in general it is not a good idea to forget to reset some pointer. Thanks, Shunning

I am a bit confused about the correct usage of the SC_REPORT_* macros. In "sysc/kernel/sc_simcontext.cpp" we have: SC_REPORT_INFO("/OSCI/SystemC","Simulation stopped by user."); The above is helpful as it produces easily parseable output. Whereas in "sysc/kernel/sc_object_manager.cpp" we have: std::string message = result_orig_string; message += ". Latter declaration will be renamed to "; message += result_string; SC_REPORT_WARNING( SC_ID_INSTANCE_EXISTS_, message.c_str()); This is not so helpful, since it is not clear where the error comes from when analysing output. A quick grep showed that there are a lot of instances where the first argument to a SC_REPORT_* macro is some ID and not the source of the error. Those IDs are resolved to error message strings, which in my opinion should go into the second argument. Could someone please clarify which way is correct? I would like to be able to handle the sc_report messages with our own message handler.

I'm trying to run uvm-systemc on macosx. Link to download: http://accellera.org/images/downloads/drafts-review/uvm-systemc-1.0-alpha1.tar.gz In the install flow, ../configure works fine, but on make i get this error: Making all in macros CCLD libmacros.laar: no archive members specifiedusage: ar -d [-TLsv] archive file ... ar -m [-TLsv] archive file ... ar -m [-abiTLsv] position archive file ... ar -p [-TLsv] archive [file ...] ar -q [-cTLsv] archive file ... ar -r [-cuTLsv] archive file ... ar -r [-abciuTLsv] position archive file ... ar -t [-TLsv] archive [file ...] ar -x [-ouTLsv] archive [file ...]make[4]: *** [libmacros.la] Error 1make[3]: *** [all-recursive] Error 1make[2]: *** [all-recursive] Error 1make[1]: *** [all] Error 2make: *** [all-recursive] Error 1 I've looked online, and it seems that it is a makefile problem. However the uvm-systemc makefile is way to complex for me to comprehend where the issue could reside. Any ideas on why is this happening? Thanks

I am writing I2C model (as per my requirement) which include master.cpp and slave.cpp. There are 2 signals: SDA and SCL, both are type of sc_inout_resolved in both the files. Connection and Port binding is done perfectly in test bench as well. I am controlling SDA & SCL in file called master.cpp. While transferring ack from slave to master, SDA will be controlled by slave.cpp (writes SDA 0). After this again master.cpp should control the SDA line for further transactions. But once controlling on SDA switches to slave.cpp, unable to control SDA again from master.cpp. Writing values(0,1) on SDA is not making any difference. I confirmed this issue using gtkwave. Am I missing anything here? Can anyone tell how to handle sc_inout_resolved between 2 models?.

I am writing I2C model (as per my requirement) which include master.cpp and slave.cpp. There are 2 signals: SDA and SCL, both are type of sc_inout_resolved in both the files. Connection and Port binding is done perfectly in test bench as well. I am controlling SDA & SCL in file called master.cpp. While transferring ack from slave to master, SDA will be controlled by slave.cpp (writes SDA 0). After this again master.cpp should control the SDA line for further transactions. But once controlling on SDA switches to slave.cpp, unable to control SDA again from master.cpp. Writing values(0,1) on SDA is not making any difference. I confirmed this issue using gtkwave. Am I missing anything here? Can anyone tell how to handle sc_inout_resolved between 2 models?.