Jump to content

Search the Community

Showing results for tags 'sc_vector'.

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


  • Accellera Systems Initiative
    • Information
    • Announcements
    • In the News
  • SystemC
    • SystemC Language
    • SystemC AMS (Analog/Mixed-Signal)
    • SystemC TLM (Transaction-level Modeling)
    • SystemC Verification (UVM-SystemC, SCV)
    • SystemC CCI (Configuration, Control & Inspection)
    • SystemC Datatypes
  • UVM (Universal Verification Methodology)
    • UVM (IEEE 1800.2) - Methodology and BCL Forum
    • UVM SystemVerilog Discussions
    • UVM Simulator Specific Issues
    • UVM Commercial Announcements
    • UVM (Pre-IEEE) Methodology and BCL Forum
  • Portable Stimulus
    • Portable Stimulus Discussion
    • Portable Stimulus 2.0 Public Review Feedback
  • IP Security
    • IP Security Assurance Whitepaper Discussion
    • IP-XACT Discussion
  • IEEE 1735/IP Encryption
    • IEEE 1735/IP Encryption Discussion
  • Commercial Announcements
    • Announcements


  • SystemC
  • UVM
  • UCIS
  • IEEE 1735/IP Encryption

Find results in...

Find results that contain...

Date Created

  • Start


Last Updated

  • Start


Filter by number of...


  • Start





Website URL












Found 12 results

  1. Hello I 'm trying to create an nxn array (nested vectors) of an rc component, with each having different r,c values ex: rc[0][0] (r=10,c=5), rc[1][1] (r=3,c=4)..... I've created the rc sub module that take the values of R and C as arguments, As follows: SC_MODULE (rc){ sca_eln::sca_terminal n; sca_eln::sca_terminal p; sca_eln::sca_r r1; sca_eln::sca_c c1; sca_eln::sca_node n1; rc( sc_core::sc_module_name nm , double r0_,double c0_) :p("p"),n("n"), r1("r1"),c1("c1"), r0(r0_),c0(c0_) { r1.p(p); r1.n(n1);
  2. Hello, I would like to create an arbitrary (random) number of processes, of the same module. So I tried with sc_vector. I can instantiate sc_module but not when there is a SC_THREAD in the module. I have the following code in my header "nodes.h" struct CNodes : sc_core::sc_module { CNodes(sc_core::sc_module_name instance); ~CNodes(void) = default; void CNodes::Init_node(int, float, float); SC_HAS_PROCESS(CNodes); private: int id = 0; // Processes and overrides void Thread_node(void); }; And the cpp files is : #include "Nodes.h" CNodes::CN
  3. I am debugging a problem with my custom datatype for sc_trace. I use my datatype for sc_signal, which is inside a sc_vector. Then I trace each signal inside the sc_vector. To narrow down my problem I removed all unnecessary parts for debugging. I still get the error, even though I'm not tracing a single signal. My MWE: main.cpp: // SystemC_FirstTest.cpp : Defines the entry point for the console application. // #pragma once //#define WIN32_LEAN_AND_MEAN //needed for tcp (winsock, ws2) #include <systemc.h> #include "globals.h" SC_MODULE(mA) { sc_inout
  4. Greetings everyone, I have a process that is sensitive to an sc_vector (specifically a vector of input ports) and was curious about how to handle the fact that values are maintained on each port in that vector on subsequent iterations of the process. This makes it very difficult to determine which values are actually new when the process is executed. I was hoping there would be a way to clear the value on a port once it had been read, but I could not find anything like this. The closest thing to a solution is to "latch" the value each time the process gets triggered and then compare the
  5. Hi, I am pretty new to systemc, and I am trying for days to instantiate an array of modules; but I am not being successfull using sc_vector. Here is the code: submodule.h #ifndef __SUBMODULE_h #define __SUBMODULE_h #include <systemc.h> //------------ DEFINITIONS --------------------------------- #define BYTE 8 typedef sc_uint<2*BYTE> uint_16b; typedef sc_uint<BYTE> uint_8b; //------------ PARAMETERS ---------------------------------- #define MAX_COUNT1 6 #define MAX_COUNT2 4 #define RESET_VALUE false //------------ MODULE -------------------------------
  6. I created vector of fifos: sc_vector<sc_fifo> fifos; and in my constructor: template <unsigned S> class my_chnl : public my_chnl_if, public sc_channel { sc_vector<sc_fifo> fifos; //vectors of fifos //----------------------------------------------------------- public: //----------------------------------------------------------- //constructor //----------------------------------------------------------- explicit my_chnl(sc_module_name nm, unsigned _size = 4) : sc_channel(nm), fifos("FIFO") { fifos.init(S, _size); } .....
  7. I need to create a TLM module (that here we will call top_level) containing an array of TLM target modules (defined by class reg). As a consequence, the top_level module should implement the tlm_bw interface, and contain an array of initiator sockets, each bound to a target socket of the reg modules. Is it possible to implement this hierarchy by using the sc_vector construct? Here is a snapshot of the code that I am trying to implement, to give a clearer idea: Top level #include "reg.h" class top_level : public sc_module , public virtual tlm::tlm_bw_transport_if<> { priv
  8. I am trying to code a very generic module that takes the number of elements of a sc_vector of sc_in from an argument. This module looks like: transformation_arbiter.h using namespace sc_core; using namespace sc_dt; class transformation_arbiter : public sc_module { public: sc_in<bool> clk; sc_vector< sc_in<bool> > enable_in; . . . private: unsigned pre_rep; public: SC_HAS_PROCESS( transformation_arbiter ); transformation_arbiter( sc_module_name trans_arbiter, unsigned ext_pre_rep ): sc_module( trans_arbiter ), pre_rep( ext_pre_rep
  9. I am trying to get an interface binded with a vector of port declared as sc_vector<sc_in<bool> > : std::vector<sc_object*> children = get_child_objects(); sc_signal<bool> *s = NULL; const char *tmp = "sc_vector"; for (unsigned i = 0; i < children.size(); i++) { if (strcmp(nm, children->basename()) == 0) { if (strcmp(children->kind(), tmp) == 0) { sc_vector<sc_in<bool> > *v = dynamic_cast<sc_vector<sc_in<bool> > * > (children); if (v != 0) {
  10. Hello, I've been trying to instantiate (if I'm not mistaken) an array of submodules that were created using sc_vector. So far, I've followed the recommendations for using custom creator functions, but I'm kind of lost at how to actually make it work. Especially with sc_bind, which keeps returning me errors. The module master houses an array of ports that will be connected to a corresponding number of slaves. Order of connection does not matter. I'm using MSVC++ 10. The code is as follows: class top : public sc_module { //Submodule declarations master master_i; sc_vector&l
  11. I am trying to use an sc_vector of modules with a custom creator to pass constructor arguments. It seems to work and run through the entire program, but at exit causes a segfault. GDB shows that this is due to to sc_vector calling the destructor of the module. I have no dynamically-allocated memory or pointers in the module. Here's the overview: outside of sc_main (global -- but I also tried inside of sc_main): -------------------------- struct create_mod { unsigned int m_arg1; unsigned int m_arg2; create_mod(unsigned int arg1, unsigned int arg2) : m_arg1(arg1), m_
  12. Hi, So I have a submodule having an array of boolean input ports. Now in the top module, I define an sc_vector of the submodule type. Also, I define an array of sc_vector signals to be bound to. Questions: Can I use an array of sc_vectors? Any conventions on using them? eg: can I write sc_vector < sc_signal <bool> > operand_vec[max_operands]; If no, then is there any work around for this? Also, I now need to assemble and bind these ports: The code below doesn't seem to work. Both the stack_cnt_vec and operand_vec are initialized properly. for(int i=0;
  • Create New...